Abstract
To overcome the challenges in MOSFET scaling, FinFETs have emerged as a probable candidate compatible with CMOS technology. Memory forms an integral part of almost all IC chips and contributes to the major share of power dissipated. Replacing MOSFET-based memory arrays with the quasi-planar FinFET helps to lower the leakage currents and thereby the power dissipation. The important criteria in the design of an SRAM cell are cell stability and cell area. The stability of the cell is determined by the static noise margin (SNM). This paper describes the modelling and simulation of a double-gate n-FinFET. It also discusses the effect of varying the gate material on the performance characteristics of the FinFET. The optimization of a 6T FinFET-based SRAM cell has also been presented. The cell optimization is in terms of the fin dimensions, namely fin width and fin pitch.
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