Design of a Radiation-Hardened SRAM Cell using 16nm Technology Node

Abstract

Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and 98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model (ASU-PTM), and the LTSpice software was used to carry out the simulations. Tools used: LTSpice v17 is the tool used to design the schematic circuits and to obtain the simulation results. The library file used to design the schematic is the 16nm technology node from the library of the Arizona State University’s Predictive Technology Model (ASU-PTM). Methods: To perform a comparative study of the 8T SRAM and 20T TICE, the schematic circuits were designed using the 16nm technology node in LTSpice. A baseline for the expected voltages of logic 0 and logic 1 is established before injecting errors at the sensitive voltage nodes of the circuit. The next step is to manually inject bit upsets at the crucial nodes of the memory cell to induce either a 0-1 upset or a 1-0 upset. The read/write operation is carried out along with the error injection to compare the error mitigation capacity of the circuits. Finally, the results are tabulated to prove that the 20T TICE is resilient to soft errors arising from exposure to high radiation. Results: During the normal operation of the 8T SRAM cell, the observed output voltage corresponding to logic 0 and logic 1 are 25mV and 780mV respectively. The voltage levels increased to 400mV during a 0-1 upset and dropped to 25mV during a 0-1 bit upset. This indicates that the cell is not reliable. In case of the 20T RHBD cell, the voltage levels for the normal operation were 5mV (logic 0) and 780mV (logic 1). The major improvement is shown in the case where the 20T TICE is injected with bit upsets, since it delivers a voltage of just 6mV during a 0-1 bit upset and maintains a voltage of 770mV during a 1-0 bit upset. Conclusion: The work performs the schematic designs for the comparison of the error mitigation capabilities of a 8T SRAM cell and a 20T TICE which is radiation hardened by design. The study proves that the 20T cell is capable of successfully mitigating both a 1-0 bit upset and a 0-1 bit upset