Design of low power SRAM cells with increased read and write performance using Read - Write assist technique

Abstract

The demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes. Process, voltage, and temperature fluctuation significantly influence several performance characteristics, making it a crucial concern in nanometer SRAM design. This study presents two novel SRAM designs that effectively decrease power consumption during read operations without compromising performance or stability. A 14T SRAM has been built with an architecture that enables single-ended write and differential read operations. In addition, a 13T SRAM has been developed using an architecture that incorporates a differential write and single-ended read operation with the assistance of a write-read circuit. The two suggested SRAM cells have been fabricated using the CMOS 45 nm technology. The provided study examines the impact of modifications in process parameters on several design metrics, including the proposed cell's read-write power and current. These metrics are then compared with those of a previously suggested SRAM cell. The read power consumption of the 14T SRAM cell is reduced by 20 %, 60.63 %, 34.73 % 53.68 %, when compared to CS6T, SS8T, SS10T, and SEW10T. For the proposed 13T SRAM, the read power consumption is reduced by 147.40 %, 230.43 %, 178.2 % 217.39 %, 30.4 % when compared to CS6T, SS8T,SS10T, SEW10T, SER11T. Also the proposed SRAM II has 106.52 % lower read power when compared with proposed 14T SRAM. Also the write power of the proposed 13T SRAM is at lower side when compared to others but at the sametime write power of proposed 14T suffers from higher power consumption. Therefore the proposed 13T SRAM has been considered for the further evaluation. The RSNM and WSNM show atleast 5 % improvement when compared to existing architectures.