Abstract

This work proposes a high-performance 16-transistor radiation-hardened SRAM cell (HP16T), which recovers from all single event upsets and from the internal node pair multiple-node upset. The proposed HP16T cell uses a separate read path through its internal nodes and demonstrates high read stability. The HP16T cell has 6.36 times higher read stability than recently proposed RHD14T cell. The write stability of the HP16T is also high, and is 1.71 times higher than that of the recently proposed HP12T cell. The HP16T cell has the shortest write access time among existing SRAM cells, and is 1.72 times smaller than that of the RSP14T cell. Compared to the existing designs, HP16T can withstand a larger amount of the critical charge, contains fewer susceptible nodes, and has the least single event upset occurrence probability. The figure of merit (FOM) is used to assess the overall performance, and the proposed HP16T exhibits the best FOM among the referenced SRAM cells.

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