Conventional Tunnel Field-effect Transistor Research Articles

Simulation of vertical ballistic quantum-barrier field-effect transistor based on undoped AlxGa1–xAs quantum nanowire

A design-topological solution for a tunnel field-effect transistor of a new type is proposed and the simulation of the transistor is performed. The device is a vertical ballistic field-effect transistor with a cylindrical metallic gate based on a cylindrical undoped AlxGa1–xAs quantum nanowire located in an Al2O3 matrix. For a given geometry of the device structure, the optimum of the fraction of aluminum in the semiconductor composition varying along the transistor channel is found, at which, unlike a conventional tunnel field-effect transistor, not only the complete suppression of the quantum barrier for electrons by a positive gate voltage is ensured, but also the minimum possible electrical resistance of the transistor channel. The current-voltage characteristics of the transistor are calculated within the framework of a rigorous quantum-mechanical description of the electron transport in its channel, taking into account the non-parabolic nature of the band structure of the semiconductor.

Bilateral sidewall engineering Si1–x Ge x iTFET for low power display application * *This work was supported in part by the Ministry of Science and Technology of Taiwan, R.O.C., under Contact MOST109–2221-E-110–018-MY3.

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve the I ON, resulting in a lower subthreshold swing average (S.S avg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that the S.S avg is improved to 21.5 mV dec−1 with an I ON/I OFF ratio of 106 at V D = 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec−1 has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

Biosensor sensitivity and steric hindrance: A comparison of InGaAs pocket and conventional TFET designs

This research article unveils a novel approach to boost the sensing ability of a biosensor by incorporating a pocket of indium gallium arsenide (InGaAs) at the source-channel junction of a tunnel field-effect transistor (TFET). The InGaAs pocket acts as a source of electrons, improving the sensitivity of the biosensor. In addition to the above, this research article also presents a comparative assessment of the proposed charge plasma-based doping less heterostructure (InGaAs pocket) TFET-based biosensor (CPDLHTFET) with a proposed (CPDLTFET) through simulations. The comparison is made based on their respective sensitivity and steric hindrance performances. Additionally, the effects of varying the pocket length and cavity length on the performance of both devices are studied and compared. The outcomes demonstrate that optimizing the InGaAs pocket and cavity length can improve sensitivity. The study also addresses the steric hindrance issue (restriction caused by the already hybridized biomolecules) and the impact on sensitivity due to probe position. The study highlights the potential of TFET-based biosensors for various biotechnology and medical diagnosis applications. Overall, this research presents a promising InGaAs pocket TFET-based design for improved performance.

Design and analysis of novel bilateral tunnelling based tunnel FET considering workfunction engineered metal strip for enhanced performance

Steep tunnelling junction is a crucial factor in nanometer regime tunnel field effect transistor (TFET) to achieve superior switching characteristics. In this regard, a novel architecture integrating low workfunction live metal strip (LWMS) in bilateral tunnelling based dual gate oxide TFET (BT DGO-TFET) is presented in this manuscript. This incorporation of LWMS results in generation of steep tunnelling junction at the channel source interface, which increases the electron accumulation, and thus boosts the tunnelling generation rate. Hence, the proposed structure accomplishes steep subthreshold swing, boosted ON-state current to OFF-state current ratio and decremented threshold voltage as compared to the conventional BT DGO-TFET. Apart from that, length, position and workfunction of LWMS has been optimized in order to achieve optimum device parameters. Finally, parameters of the proposed architecture have been compared with the parameters of the conventional BT DGO-TFET and TFETs in the existing literature. The proposed device is observed to be highly suitable for analogue/RF and low power switching applications.

Performance Boost of Si TFETs by Insertion of III–V Dipole Formation Layer: A First Principle Study

Silicon channel tunnel field-effect transistors (TFETs) are known to exhibit low ON-state current due to the wide indirect band gap. In this work, to achieve high ON-state current, we propose a Si TFET with an ultra-thin dipole formation layer (DFL) inserted at the source/channel junction. The inserted DFL forms charge transfer dipoles at the interface, resulting in a staggered band gap. As the consequence, the effective tunnel barrier for electrons is significantly lowered so that ON-state current increases by orders of magnitude. To analyze the characteristics of DFL-inserted Si TFETs, we have solved nonequilibrium Green’s function (NEGF) and Poisson’s equation using density functional theory (DFT) Hamiltonians. We demonstrate that DFL-inserted Si TFETs show boosted performance over conventional TFETs, exhibiting high ON-state current and steep subthreshold swing (SS).

Performance investigation of a charge plasma tunnel FET with SiGe source pocket as a photosensor

This study investigates a highly sensitive and low-power photosensor using a pocket-based charge plasma tunnel field-effect transistor (PCPTFET) structure for visible light detection. Here, zinc oxide, the transparent optical region over the channel, is the catalyst for the photo-sensing operation. When light strikes the sensitive portion of the device, creating optical charge carriers in the illumination region and substantially increases the device’s conductance. The analysis of various parametric and structural variations like intensity power density (Pj ), optical wavelength (λ), drain to source voltage (V DS), incident angle (θ), and silicon body thickness (t si) have been investigated for the reported pocket-based charge plasma TFET (PCPTFET) photosensor. Further, the PCPTFET’s superior performance as a highly sensitive photosensor is revealed by comparing the several optical figures of merit (FOM) with conventional tunnel field-effect transistor. The reported photosensor provides much-improved responsivity (R) of 1.52 A W−1 and quantum efficiency (η) of 4.96.

Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor

Tunnel field-effect transistors (TFETs) have garnered great interest as an option for the replacement of metal–oxide–semiconductor field-effect transistors owing to their extremely low off-current and fast switching suitable for low-power-consumption applications. However, conventional doped TFETs have the disadvantage of introducing undesirable random dopant fluctuation (RDF) events, which cause a large variance in the threshold voltage and ambipolar leakage current at negative gate voltages. In this study, a simple approach for charge plasma-based doping-less TFETs (DL-TFETs), including the Ge/Si bilayer frame, which affects the RDF and low on-current issues, was developed by the commercially available Silvaco Atlas device simulator. The use of the Ge/Si bilayer enhances the on-current and point subthreshold swing to 1.4 × 10−6 A and 16.6 mV dec−1, respectively. In addition, the dependencies of the Ge/Si junction boundary position and Ge content were examined systematically to attain a firm understanding of the electrical features in DL-TFETs.

Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study

The steep sub-threshold swing of a tunneling field-effect transistor (TFET) makes it one of the best candidates for low-power nanometer devices. However, the low driving capability of TFETs prevents their application in integrated circuits. In this study, an innovative gate-all-around (GAA) TFET, which represents a negative capacitance GAA gate-to-source overlap TFET (NCGAA-SOL-TFET), is proposed to increase the driving current. The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design (TCAD) simulations. The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes. In addition, due to the negative capacitance effect, the surface potential of the channel can be amplified, thus enhancing the driving current. The gate-to-source overlap (SOL) technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon–germanium heterojunction. By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness, a sufficiently large on-state current of 17.20 μA can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade. Finally, the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem, achieving a driving current that is comparable to that of the traditional complementary metal–oxide semiconductor devices.

Modelling and Simulation of Ge Absorber-based Tunnel Field-Effect Phototransistor at 1550 nm

In this article, a semi-analytical model for germanium absorber-based SOI-tunnel field-effect phototransistor at 1550 nm has been proposed. The model works efficiently for a wide range of intensities i.e. 10−2 to 102 µW/µm2 under the application of a very low gate voltage of 0.54 V. Exhaustive simulations using numerical ATLAS 2D device simulation tool with LUMNINOUS optical module have been carried out to propose the merit of tunnel field-effect transistors (TFETs) over metal oxide semiconductor field effect transistors (MOSFETs) for optical applications. The proposed TFET design provides a way to assist the ultrasensitive optical interconnects at a very low gate bias of 0.54 V with a maximum sensitivity of 1.5 × 107, responsivity of 270 mA/W, and detectivity of 3.5 × 1012 Jones at low power density of 0.01 µW/µm2. The TFET performance has further been improved by introducing a heavily doped pocket in between source and channel, which serves as a potential alternative for photodetector applications. The proposed pocket-doped TFET design offers significant improvements in device optical response with optimized sensitivity of 4.1 × 107, a responsivity of 772 mA/W, and a detectivity of 9.9 × 1012 Jones at an optical intensity of 0.01 µW/µm2, gate bias of 0.45 V, and drain voltage of 0.6 V. Transient analysis has been carried out to optimize the response time of the phototransistor for both Ge-gated conventional TFET and pocket-doped architecture and the fall time of ∼0.22 ms has been achieved.

Novel attributes of a dual pocket tunnel field-effect transistor

In this paper, we propose the application of a dual pocket adjacent to the source in a tunnel field effect transistor (TFET) to improve its electrical characteristics. Using two-dimensional device simulations, we demonstrate that if appropriate doping concentration and length are chosen for the dual pocket, then a sharp curvature is obtained in the energy bands at the onset of tunneling. Consequently, a smaller tunneling width and higher band-to-band tunneling are obtained in a dual pocket TFET (DP-TFET). We demonstrate that the proposed DP-TFET exhibits a 64% smaller average subthreshold swing (SS) compared to a conventional TFET and a 39% smaller average SS compared to a TFET in which a single fully depleted counter-doped pocket adjacent to the source is added. Moreover, the proposed technique of inserting a dual pocket is effective at lower supply voltage (V DD = 0.5 V). Therefore, we can obtain a high ON-current to OFF-current ratio at lower supply voltages and the proposed technique can be employed in future TFETs for low power applications.

Electrical Performance Enhanced Doping Less Tunnel Field Effect Transistor by Metal Electrode Work Function Engineering

Tunnel field effect transistor (TFET) has been proposed as one of the promising alternative devices to MOSFET since it has low power consumption and excellent subthreshold swing (SS) characteristics of less than 60 mV / dec. However, conventional TFET fabrication requires ion implantation process to form p-i-n structure in active region, which induces a random distribution of dopant atoms. In the nm-scale device, even a small number of dopant atom dispersion can cause electrical characteristic variations such as threshold voltage (Vt)1, so alternative method for forming p-i-n region instead of doping process is needed.Doping-less TFET (DL-TFET) introduces charge plasma concept2 that controls carrier concentration of Si region by band alignment in MOS contact not by doping process, so random dopant fluctuation (RDF) issue can be solved. Since the active region carrier concentration is determined by the work function of the metal electrode, it is necessary to analyze the device performance by the metal work function condition. In this work, we manufactured doping-less TFET with adapting various metal work function to enhance electrical performance, and conducted CV measurement in MOS structure to confirm Si band bending and charge plasma by analyzing flat band voltage (VFB).DL-TFET was fabricated on SOI wafer and the overall structure is shown in Fig. 1. (a). In the case of the source region, the metal work function must be larger than that of Si to form the p-type active area, and drain region, on the contrary, must have smaller work function for n-type active region. Obviously, gate electrode work function has similar work function to intrinsic Si. For fabricating DL-TFET, we conducted reactive ion etch (RIE) process to define Si active layer and formed gate oxide (SiO2) by thermal oxidation. Then, we deposited gate metal and removed source / drain region oxide for contact hole. Spacer oxide was deposited using PECVD to isolate each metal electrode, finally we deposited source / drain metal. IV characteristics are shown in Fig. 1. (b), (c) when Pt / W / Al is applied at source / gate / drain area and we compared IV curve of various metal electrode and thermal conditions.In addition, to confirm whether the charge plasma was formed as intended, we fabricated MOS capacitor with 10 nm oxide thickness as shown in Fig. 1. (d). Through frequency sweep, we determined suitable bias frequency and conducted CV measurement (see Fig. 1. (e), (f), (g)). Band bending and charge plasma were confirmed by evaluating VFB shift depending on work function of each MOS gate material (see Fig. 1. (h)). Finally, we discussed the optimal metal electrode combination in terms of ambipolar current, off current, on current and SS. Key Words: Charge plasma, Doping-less TFET, Work function, CV measurement References Changho Shin, Jeong-Kyu Kim, Gwang-Sik Kim, Hyunjae Lee, Changhwan Shin, Jong-Kook Kim, Byung Jin Cho, and Hyun-Yong Yu, “Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal–Interlayer–Semiconductor Source/Drain,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, No. 11, pp 4167-4172, Nov 2016. doi: 10.1109/TED.2016.2606511 Raymond J. E. Hueting, Bijoy Rajasekharan, Cora Salm, and d Jurriaan Schmitz, " The Charge Plasma P-N Diode" IEEE ELECTRON DEVICE LETTERS, vol. 29, issue 12, pp 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2021, the MOTIE (Ministry of Trade, Industry & Energy 20010836) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Temperature analysis on electrostatics performance parameters of dual metal gate step channel TFET

In this research work, a device structure modification for a doped tunnel field-effect transistor (TFET) is proposed with gate engineering at the gate electrode to overcome the limitations of conventional TFET. Moreover, the temperature is one of the most effective parameters which affects the device performance. In this concern, a brief research of temperature impact on DC characteristics, analog/RF parameter, and linearity parameters has been performed for the proposed device at temperatures ranging from 250K to 400K with an interval of 50K. OFF-state current is more sensitive towards high temperature which results in high ambipolar behavior due to thermal leakage current which degrades switching speed. So, the impact of temperature on output current at low applied voltages is also studied using different models like BTBT, SRH, and TAT. However, ON-state current shows a negligible impact of temperature variation that makes a very prominent device for low-power high-frequency applications. This type of detailed study on all the performance parameters of the proposed device is beneficial from a design point of view.

Doping-less tunnel field-effect transistors by compact Si drain frame/Si0.6Ge0.4-channel/Ge source

Tunnel field-effect transistors (TFETs) have attracted immense interest as a promising alternative to complementary metal–oxide semiconductors for low-power-consumption applications. However, conventional TFETs introduce both random dopant fluctuations and ambipolar current issues at negative gate voltages for sub-6-nm technology nodes. In this study, we address the performance of charge plasma-driven doping-less TFETs, including sub-3-nm thick compact drain (CD) geometry/SiGe-channel/Ge source layers for suitable bandgap engineering. An ultrathin CD frame and heteromaterials are adopted for use as channels/sources to improve the ambipolarity and ON-state features, respectively. Simulation demonstrates a clear reduction in the ambipolar current from 3.3 × 10−14 to 3.0 × 10−17 A at gate (VG)/drain (VD) voltages of −1.5/1.0 V and an enhancement in the ON-current from 2.0 × 10−5 to 8.6 × 10−5 A at VG = 1.5 and VD = 1.0 V, compared with conventional TFETs. In addition, diverse fabrication-friendly metals applicable to industry fieldwork sites are tested to determine how the metal work functions influence the outputs. The use of Ti/W/Ni as the drain/channel/source materials, respectively, yields an enhanced ambipolar current of 1.2 × 10−20 A and an ON-current of 3.9 × 10−5 A.

Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction.

It is well known that the vertical tunnel field effect transistor (TFET) is easier to fabricate than the conventional lateral TFETs in technology. Meanwhile, a lightly doped pocket under the source region can improve the subthreshold performance of the vertical TFETs. This paper demonstrates a dual material gate heterogeneous dielectric vertical TFET (DMG-HD-VTFET) with a lightly doped source-pocket. The proposed structure adopts a GaSb/GaAs0.5Sb0.5 heterojunction at the source and pocket to improve the band-to-band tunneling (BTBT) rate; at the same time, the gate electrode is divided into two parts, namely a tunnel gate (M1) and control gate (M2) with work functions ΦM1 and ΦM2, where ΦM1 > ΦM2. In addition, further performance enhancement in the proposed device is realized by a heterogeneous dielectric corresponding to a dual material gate. Simulation results indicate that DMG-HD-VTFET and HD-VTFET possess superior metrics in terms of DC (Direct Current) and RF (Radio Frequency) performance as compared with conventional VTFET. As a result, the ON-state current of 2.92 × 10−4 A/μm, transconductance of 6.46 × 10−4 S/μm, and average subthreshold swing (SSave) of 18.1 mV/Dec at low drain voltage can be obtained. At the same time, DMG-HD-VTFET could achieve a maximum fT of 459 GHz at 0.72 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 35 GHz at Vgs = 0.6 V, respectively. So, the proposed structure will have a great potential to boost the device performance of traditional vertical TFETs.

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Performance Improvement of Double-Gate TFET Using Metal Strip Technique

In order to overcome the limitations of a tunnel field-effect transistor (TFET) and to enhance its performance, the use of a low work function live strip (LWLS) in a conventional double-gate TFET (DG-TFET) is proposed in this paper. In this novel DG-TFET architecture, named as LWLS-DG-TFET, a metal strip has been implanted in the oxide layer near the source-channel interface. This technique increases the tunneling rate and thus improves the on-current conduction. In this work, a conventional DG-TFET structure in the presence of a metal live strip is studied and analyzed in detail. Moreover, the position of LWLS has been fixed to optimize the TFET performance. The TCAD simulation results show the DC and analog/RF performance improvement of the proposed LWLS-DG-TFET compared to the conventional DG-TFET.

Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor

To overcome the fabrication complexity and achieve a better switching ratio is a major grave concern for applications in semiconductor devices. In this regards, a novel stack gate-oxide junctionless double-gate tunnel field effect transistor with low work-function livestrip (LWLS-SGO-JL-TFET) has been investigated in this manuscript. This structure serves as an alternative solution to improve the performance of device. For this, device structure has comprised of two isolated gates such as polarity gate and control gate with the platinum (work-function = 5.93 eV) and hafnium (work-function = 4.3 eV) respectively, over the N+-type doped silicon substrate for the formation of Tunnel Field Effect Transistor as a like doped conventional TFETs (Tunnel Field Effect Transistors) to overcome fabrication complexity. Since ON state current plays important role in switching ratio and subthreshold swing. Therefore, a dual layer oxide (stack) has introduced in junctionless TFETs to get further improvement in ON state current due to the better capacitive coupling between gate and substrate. Under this condition, the performance improvement is still required of dual oxide juntionless TFETs. Hence, a live strip has inserted at the source side in dual oxide layer to improve the ON state current which helps in gain of device and design of analogue and RF circuits. Moreover, we have also examined the impact of low work-function of live strip on dual oxide Junctionless TFETs in terms of DC, analog/RF and linearity figures of merit (FOMs) of the device. All simulation have been carried out using the technology computer aided design (TCAD) tool. This study shows that proposed device is an appropriate for ultra low power high frequency applications.

Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

In this paper, we propose, design and simulate a new double gate (DG) tunnel field effect transistor (TFET), using germanium (Ge) source, dual dielectric gate oxide, gate/drain underlap and a metal drain. The device is designed to address two important issues of a conventional TFET, that is, the poor ON current (ION) and the presence of ambipolar conduction. In the proposed device, the use of Ge material for the source region and a dual dielectric gate oxide enhances the ION significantly and employing metallic drain and a gate-drain underlap fully suppresses the ambipolarity conduction. This can be attributed to the formation of a Schottky barrier at channel/drain interface. Two-dimensional (2D) calibrated simulation studies have been performed using the commercial TCAD device simulator. The results have shown that the ION has improved by almost ~3 orders whereas ambipolar current is completely suppressed in the proposed device in comparison to the conventional DG-TFET. Further, it has been found that the proposed device has a subthreshold slope (SS) of 35 mV/dec, ION of ~2×10−4 A/ μm and the ION to IOFF ratio (ION/IOFF) of ~1013. The proposed device performance can be improved further by optimizing various device parameters, like underlap length etc. A flow chart mentioning the key fabrication steps has also been proposed to fabricate the proposed device.

Design and performance optimization of thin film tin monoxide (SnO)/silicon electron–hole bilayer tunnel field-effect transistor

This paper presents a novel thin film electron–hole bilayer tunnel field-effect transistor based on an oxide semiconductor tin monoxide (SnO)/silicon heterojunction (TFBTFET), which delivers low-power high switching speed characteristics. SnO has an intrinsic p-type profile, which provides desirable properties for application in thin film tunnel transistors and liquid crystal displays. Unlike conventional tunnel field-effect transistors with limited horizontal tunneling direction, the tunneling window of the TFBTFET is created along the channel length in the vertical direction, leading to significantly increased drain drive current. The results demonstrate that the steep transition of the current from off-state to on-state delivers subthreshold swing of 5 mV/dec with on-state current of 3.03 × 10−5 (A/µm), off-state current of 5.1 × 10−14 (A/µm) and on/off current ratio of 5.94 × 108. The impact of critical scaling of design parameters on the electrical performance of the device is comprehensively investigated by calculating the coefficient of variation (CV), expressed as a percentage, of the main electrical measures. The 2D variation contour of required voltage for the onset of band-to-band tunneling is computed as a function of the top and bottom gate work function to determine an optimum value yielding superior electrical performance. Moreover, CV analysis reveals that the off-state current and subthreshold swing are relatively insensitive to the variation in gate length, which indicates the potential for application of the device in integrated circuits with superior efficiency.

A SPICE model of p‐channel silicon tunneling field‐effect transistors for logic applications

AbstractIn this study, we propose a SPICE model of p‐channel silicon tunneling field‐effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p‐TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c‐TFET) inverters, c‐TFET NAND gates, and c‐TFET NOR gates using our TFET model. Our simulation shows that a c‐TFET inverter can be operated at VDD as low as 0.3 V and that c‐TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.