Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study

Abstract

The steep sub-threshold swing of a tunneling field-effect transistor (TFET) makes it one of the best candidates for low-power nanometer devices. However, the low driving capability of TFETs prevents their application in integrated circuits. In this study, an innovative gate-all-around (GAA) TFET, which represents a negative capacitance GAA gate-to-source overlap TFET (NCGAA-SOL-TFET), is proposed to increase the driving current. The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design (TCAD) simulations. The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes. In addition, due to the negative capacitance effect, the surface potential of the channel can be amplified, thus enhancing the driving current. The gate-to-source overlap (SOL) technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon–germanium heterojunction. By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness, a sufficiently large on-state current of 17.20 μA can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade. Finally, the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem, achieving a driving current that is comparable to that of the traditional complementary metal–oxide semiconductor devices.