Conventional 6T Research Articles

A read-disturb-free stable low power and high-density GNRFET 6T SRAM with multi-VT technology

PurposeThe performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.Design/methodology/approachThis study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.FindingsThe GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.Research limitations/implicationsNano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.Practical implicationsGNRFET devices are suitable for implementing low power and high density SRAM cell.Social implicationsThe conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.Originality/valueThis paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield

This article presents a new resistive random access memory (RRAM)-based average 7T1R nonvolatile static random access memory (nvSRAM). This multiple sharing (MS) 7T1R uses MS schemes in which some of the transistors play various roles. Therefore, the MS-7T1R can perform a decoupled read, enhance write capability, and improve the restore yield with a small area cost. Furthermore, the MS-7T1R can offer two alternative modes, i.e., a high speed and a stable mode. Compared with existing technologies, such as the previous 6T-based nvSRAMs, the results show that the proposed architecture provides a remarkable restore yield and ~154% improvement in the read static noise margin (at TT corner and stable mode). In addition, the read delay improves by ~23% (at TT corner and high-speed mode). The write “1” problem of the single bitline is effectively resolved with our proposed write strategy. The static write margin of “1” is improved by ~88.6% compared with the conventional 6T ( $\beta =4$ ) at a power of 1.2 V. In addition, dynamic power is effectively reduced by the use of the single bitline and sub-word-line driver technology.

Design of a Stable Low Power 11-T Static Random Access Memory Cell

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [Formula: see text] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability

Scaling of supply voltage is a well-received approach to reduce power consumption in Static Random Access Memory (SRAM). However, conventional 6T and 8T SRAMs suffer from degraded stability due to random process variations, thereby limiting voltage scaling. It has been observed that Schmitt Trigger (ST) based SRAMs exhibit much better stability than conventional 6T and 8T SRAMs. However, ST based SRAMs inherently suffer from poor write-ability and therefore, exhibit overall higher VMIN. In this work, we propose a twelve-transistor ST based SRAM bit cell, aimed at enabling process-variation-tolerant write-ability, consequently allowing an overall reduction in VMIN and energy per operation. Simulations on the 32 ​nm process node demonstrate that the proposed SRAM allows up to 188 ​mV reduction in VMIN over previous ST bit cells. This translates to up to 3.65 × and 1.91 × lower energy consumptions than conventional 6T and ST-based SRAMs respectively. With large reductions in energy per operation at VMIN, the proposed SRAM is suitable for ultra-low power applications.

CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays

Rapid development in deep neural networks (DNNs) is enabling many intelligent applications. However, on-chip training of DNNs is challenging due to the extensive computation and memory bandwidth requirements. To solve the bottleneck of the memory wall problem, compute-in-memory (CIM) approach exploits the analog computation along the bit line of the memory array thus significantly speeds up the vector-matrix multiplications. So far, most of the CIM-based architectures target at implementing inference engine for offline training only. In this article, we propose CIMAT, a CIM Architecture for Training. At the bitcell level, we design two versions of 7T and 8T transpose SRAM to implement bi-directional vector-to-matrix multiplication that is needed for feedforward (FF) and backprogpagation (BP). Moreover, we design the periphery circuitry, mapping strategy and the data flow for the BP process and weight update to support the on-chip training based on CIM. To further improve training performance, we explore the pipeline optimization of proposed architecture. We utilize the mature and advanced CMOS technology at 7 nm to design the CIMAT architecture with 7T/8T transpose SRAM array that supports bi-directional parallel read. We explore the 8-bit training performance of ImageNet on ResNet-18, showing that 7T-based design can achieve 3.38× higher energy efficiency (∼6.02 TOPS/W), 4.34× frame rate (∼4,020 fps) and only 50 percent chip size compared to the baseline architecture with conventional 6T SRAM array that supports row-by-row read only. The even better performance is obtained with 8T-based architecture, which can reach ∼10.79 TOPS/W and ∼48,335 fps with 74-percent chip area compared to the baseline.

A Novel Design for a Low-Power High-Speed Robust Supply-Gated-Sleep 6T SRAM Cell

In recent, the low-power and high- speed memory is required because of this extensive use in the electronic portable equipments. The power consumption and speed are the major factor for memory design techniques. This paper presents design of the proposed circuit, and the implementation for proposed 6T SRAM with a Transmission gate and supply-gated technology. In this paper the comparative analysis on different parameters of conventional 6T SRAM, existing 6T SRAM and the proposed 6T SRAM are performed. This new approach can reduce the total power and total delay compared to conventional and existing 6T SRAM. All the experimental works are done by Microwind and DSCH 2.7 version software tool.

Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed. The conventional 6T TFET SRAM cell is designed using DG TFET of 30 nm. For the circuit simulation, the symbol of DG TFET is developed with the help of a look-up table based Verilog-A code. The radiation induced single event upset (SEU) causes a change in the stored data of SRAM cell. In order to improve the SEU sensitivity, the radiation hardening-by-design technique (RHBD) is introduced in 6T TFET SRAM cell by connecting the RC feedback loop between the two cross coupled inverters. The standby power of the TFET SRAM cell is calculated and compared before and after the radiation mitigation technique insertion.

Implementation and modeling of low power sleepy stack SRAM cell

for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

High Stable and Low Power 10T CNTFET SRAM Cell

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

Design of Low Power Memory Architecture using 10t Sram Array

The main aim of electronics is to design low power devices due to the prevalent usage of powered gadget. Ultra low voltage operation of memory cells has become a subject of a lot of interest because of its applications in terribly low energy computing. The stable operation of static random access memory (SRAM) is important for the success of low voltage SRAM and it is achieved by parameter variations of scaled technologies. The power consumption and access time of the SRAM is also a complex parameter due to the unavoidable switching activities of the number of transistors used for different blocks like, SRAM cell, access transistors, pre-charge circuit, sense amplifier and decoders. It has been shown that conventional 6T SRAM fail to achieve low power and delay operation. The proposed 10T SRAM design gives an approach towards the hold power dissipation. The designed circuit has 10 transistors out of that 2 transistors are used as sleep transistor. The sleep transistors are used as switches. Such as header and footer switches and the switches are turned on during active mode of operations and turned off during idle or standby mode of operations. The designed SRAM cell also has conducting pMOS circuit, which can reduces the total power dissipation. The SRAM cell is simulated by using Cadence tool. A supply voltage of 1.8V is used which makes it enough for low power applications. The power obtained as 761.7mW, which reduces 15% of conventional 6T SRAM design. The delay obtained as 125.6ns, which reduces 45% of conventional 6T SRAM.

Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications

ABSTRACTWith rapid growth of Internet of Things, more and more devices are getting connected, which results in generation of large amount of data. To convert this collected raw data into useful information, it needs to be processed. However, during processing a significant amount of energy is spent in bringing data from off-chip non-volatile memory to on-chip memory. In addition, these devices are generally operated in ‘Normally OFF’ mode, which requires energy intensive boot process for waking up. Addressing these issues, Magnetic Tunnel Junction offers features like non-volatility and high integration density, which allows storage of data and instruction closer to the core. Therefore, this work proposes a hybrid multibit SRAM cell, which integrates MTJ with conventional 6T SRAM cell. The proposed SRAM cell supports multiple bit storage within a single cell. However, one of the critical issues with the MTJ is high-energy consumption while storing data. Hence, we also propose a store assist circuit for multibit SRAM cell, which asynchronously terminates the store operation after its completion to reduce the power consumption. Our simulation results show that the store assist circuit results in reduction of store energy by 35% and 72% when compared with existing multibit non-volatile SRAM.

7T Based SRAM Topologies with Low Power and Higher SNM

Now the era is of electronic gadgets like processors and portable devices, in which Memory plays a significant role through the usage of Static RAMs (SRAMs).Hence designing of Low power SRAM is immense for applications. But the design of SRAM is involved in higher power requirement. So there is still scope for adequate Low power Memory Array design. The Main Moto of this paper is involved in designing & Simulating Low Power 16x16 SRAM Arrays using 7T SRAM cells based on Conventional, Self Controllable Voltage (SVL) & Improved Self Controllable Voltage (I-SVL) methods. Also Comparative Power and SNM Analysis is carried between Conventional 7T, 7T-SVL and 7T-ISVL based Arrays. The Proposed Array using 7T Cell consumes 6.24mW which is 67.64% lesser than the Array design [2].Also I-SVL based 7T SNM is better than the SVL-7T and 7T based cell.The proposed work is carried using cadence virtuoso tool with standard library gpdk 180nm.Also Proposed Array based on I-SVL is efficient in terms of power. The proposed Cell SNM resulted in 68.57% higher in comparison with existing cell of 8T and 10T [3].

An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network

In this paper, a novel single ended PPN based 10T static random access memory (SRAM) with high read stability is presented. The proposed cell is energy efficient with double ended write, and single-ended read decoupled circuit for wireless sensor networks. The proposed 10T SRAM cell has a significant improvement in READ and WRITE stability with the least energy consumption. To evaluate the performance of the cells static noise margin, delay, power dissipation, leakage current, and area are calculated using the cadence environment at a standard CMOS 45 nm process technology. The simulation results show that it has enhancement of 83.4%, 50.14%, 43.3%, 50.14% and 3.09% on read SNM when compared with the conventional 6T, ST11T, ST1, ST2, and PPN 10T respectively at 1 V supply voltage. The proposed cell also achieves write SNM of 1.29×, 1.12×, and 1.18× higher compared to 6T, PPN10T, and ST11T, respectively. For a better perspective, we have proposed a figure of merit considering all the performance parameters, and it is observed that the proposed cell has better the FOM as compared to all other considered cells.

A new 7T SRAM cell in sub‐threshold region with a high performance and small area with bit interleaving capability

In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper performance in bit-interleaving structure and sub-threshold region in cost of more area consumption. This study presents a new bit-interleaving 7T SRAM cell which occupies less area consumption and has a better performance when compared with other 9T, 10, and 12T bit-interleaving cells. The suggested 7T cell is simulated with HSPICE in 32 nm technology and with multi-Vt transistors considering LP, HP, and standard models for HVt, LVt, and SVt transistors, respectively. The simulation results demonstrate the performance superiority of authors' proposed cell compared with its counterparts. Moreover, the simulation results (VDD = 0.5 V) show the suggested cell in comparison with conventional 6T cell improves read, hold, and write power consumptions 91.42, 91.93, and 68.7%, respectively. Also, cell stability (RSNM) and write margin (WM) parameters improve 172 and 67.2%, respectively.

Parameters for Stability of Reconfigurable Memory and 6T SRAM Cell

As the technology is improving, channel length of MOSFET is scaling down. In this environment stability of SRAM becomes the major concern for future technology. Static noise margin (SNM) plays a vital role in stability of SRAM. This paper gives an introduction to the reconfigurable memory and 6T SRAM cell. It includes the implementation, characterization and analysis of reconfigurable memory cell and its comparison with the conventional 6T SRAM cell for various parameters like read margin, write margin, data retention voltage, temperature and power supply fluctuations and depending upon these analysis we find SNM for 6T and 8T SRAM cell. The tool used for simulation purpose is IC Station by Mentor Graphics using 350nm technology at supply voltage of 2.5volts.

High Stable and Low Power 8T CNTFET SRAM Cell

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

A 7T Security Oriented SRAM Bitcell

Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel PA attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over $1000 {\times }$ lower write energy standard deviation between write “1” and “0” operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%–53% write energy reduction and a 19%–38% reduced write delay compared to other PA resistant SRAM cells.

Stability analysis of Sub-threshold 6T SRAM cell at 45 nm for IoT application

In ultra-Low power application the supply volt- age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv.

Transmission gate‐based 9T SRAM cell for variation resilient low power and reliable internet of things applications

Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.