A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability

Abstract

Scaling of supply voltage is a well-received approach to reduce power consumption in Static Random Access Memory (SRAM). However, conventional 6T and 8T SRAMs suffer from degraded stability due to random process variations, thereby limiting voltage scaling. It has been observed that Schmitt Trigger (ST) based SRAMs exhibit much better stability than conventional 6T and 8T SRAMs. However, ST based SRAMs inherently suffer from poor write-ability and therefore, exhibit overall higher VMIN. In this work, we propose a twelve-transistor ST based SRAM bit cell, aimed at enabling process-variation-tolerant write-ability, consequently allowing an overall reduction in VMIN and energy per operation. Simulations on the 32 ​nm process node demonstrate that the proposed SRAM allows up to 188 ​mV reduction in VMIN over previous ST bit cells. This translates to up to 3.65 × and 1.91 × lower energy consumptions than conventional 6T and ST-based SRAMs respectively. With large reductions in energy per operation at VMIN, the proposed SRAM is suitable for ultra-low power applications.