Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

M Pown,B Lakshmi

doi:10.1109/jeds.2020.3002265

Abstract

This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed. The conventional 6T TFET SRAM cell is designed using DG TFET of 30 nm. For the circuit simulation, the symbol of DG TFET is developed with the help of a look-up table based Verilog-A code. The radiation induced single event upset (SEU) causes a change in the stored data of SRAM cell. In order to improve the SEU sensitivity, the radiation hardening-by-design technique (RHBD) is introduced in 6T TFET SRAM cell by connecting the RC feedback loop between the two cross coupled inverters. The standby power of the TFET SRAM cell is calculated and compared before and after the radiation mitigation technique insertion.

Highlights

Radiation induced single event upset (SEU) is a soft error caused by a transient signal induced by an energetic particle strike
The collected charge (Qcoll) of electron-hole pair can change the state of the memory cell, register, latch or flip flops, only if it is greater than the critical charge (Qcrit), which is the minimum charge required to trigger a change in the data state [1], [2]
The performance of 6T double-gate tunnel field effect transistor (DG Tunneling field effect transistors (TFETs)) SRAM cell is analyzed by injecting the transient current source at the struck node

Summary

INTRODUCTION

Radiation induced single event upset (SEU) is a soft error caused by a transient signal induced by an energetic particle (e.g., protons, neutrons, alpha particles or other heavy ions) strike. A technique, commonly known as radiation hardening-bydesign (RHBD) is used to mitigate the soft error caused by the ionizing radiation in circuit level [13]. To mitigate the SEU effect in FinFET based circuits, the radiation hardened circuits have been reported [17], [18]. The soft error generation and propagation in Si FinFET, III-V FinFET, and III-V Hetero-junction tunnel FET (HTFET) are investigated using device and circuit simulation [26]. The soft error performance, its mitigation technique and the power consumption before and after the radiation are studied in 6T SRAM cell using DG (Double Gate) TFETs. This paper is organized as follows: Section II describes the DG TFET device structure and simulation methodology.

METHODOLOGY

CONCLUSION