Design and analysis of low power SRAM cells

Abstract

The rapid growth of portable battery operated devices has made low power IC design a priority in recent years. Embedded SRAM units have become an integral part in modern SoCs. Conventional SRAM cell designs are power hungry and poor performers in this new era of fast mobile computing. In this paper, low power SRAM cell designs have been analyzed for power consumption, write delay and write power delay product. Gated VDD and MTCMOS design techniques have been employed to reduce the power consumed by the SRAM cell. These designs are compared with the conventional 6T SRAM cell. The results show that the MTCMOS based SRAM cell is the best performer in terms of power consumption and write delay. It uses 38.1% less power than the conventional 6T SRAM cell. Furthermore, the MTCMOS based SRAM cell is 18.18% faster than the conventional 6T SRAM cell. The Gated VDD SRAM cell also performs well using 16.8% less power than the conventional 6T SRAM cell and is 13.03% faster than the conventional 6T SRAM cell.