Characterization of 8T SRAM cells using 16 nm FinFET technology

Abstract

SRAMs are faster and more reliable which are often used as memory cache in digital processors for high speed operation. Conventional 6T SRAM cell suffers from access transistor sizing conflict resulting in a trade-off between read stability and write ability. This paper presents the characterization of four 8T SRAM cell structures - Conventional 8T SRAM cell, Single Ended 8T SRAM cell, 8T SRAM cell using two conducting p-type transistors and 8T SRAM cell using transmission gate between the cross-coupled inverters using 16 nm FinFET technology at a supply voltage 0.85 V. The stability performance parameters RSNM and WSNM are analyzed. HSPICE simulation results show that FinFET based SRAM designs provide better performance compared to CMOS based SRAM designs at technology nodes below 32 nm. Conventional 8T SRAM cell provides better RSNM and WSNM of 261.81 mV and 273.58 mV compared to the other structures which either degrade RSNM or WSNM or depend on proper transistor sizing for successful operation of the SRAM cell.