Analysis of Higher Stable 9T SRAM Cell for Ultra Low Power Devices

Abstract

VLSI designers are inspired by the widespread use of portable low power devices. In this paper, a 9T SRAM cell has been analyzed and implemented at 45 nm technology node with Cadence virtuoso tool. The read stability and write ability of considered cell is improved by 2.05\(\times \) and 1.13\(\times \) in comparison to conventional 6T SRAM cell. The write access time of 9T SRAM cell is 3.37\(\times \) and 2.94\(\times \) better in comparison of conventional 6T and differential (DF) 8T SRAM cell respectively. Furthermore, the write power of 9T SRAM cell is reduced by a factor of 2.07\(\times \) and 1.77\(\times \) as comparison of conventional 6T and Differential 8T SRAM cell respectively at 0.5 V supply voltage. The data retention voltage of 9T SRAM cell is better at all corners in comparison of conventional 6T and differential 8T SRAM cell respectively. The 9T SRAM cell may be utilized in IoT based devices such as medical equipments, space applications, etc.