Design of differential TG based 8T SRAM cell for ultralow-power applications

Abstract

Low power cache memory in a system on chip is in high demand today. With the lowering of MOSFET’s channel length, low-power SRAM design has become a more challenging task. This paper presents differential 8T SRAM cell with minimum power utilization. The proposed cell has one pair of transmission gate as access switches. Due to use of TG instead of pass gate access transistor its write access time (TWA) is short. The low power consumption of the cell is due to stacking effect. This paper compares design metrics of the proposed cell with conventional 6T (CON6T) and ZIGZAG 8T (ZG8T) SRAM cells. The proposed 8T SRAM cell shows 1.15×/1.17× improvement in TWA as compared to CON6T/ZG8T at a penalty of 2.65×/2× in read access time (TRA). The proposed cell consumes 3.22× less hold power compared to both CON6T and ZG8T SRAM cells. And the proposed cell consumes 4.41× (4.44×) less write power as compared to CON6T (ZG8T) SRAM cell. Our proposed cell takes 1.37× lower chip area as compared to ZG8T cell at the expense of 1.49× higher area as compared to CON6T SRAM cell. The proposed cell also achieves 1.5×/3× higher stability during write operation as compared to CON6T/ZG8T SRAM cell, respectively. Read static margin of the proposed cell is same as CON6T but 3.2× lower than ZG8T SRAM cell.