Simulation and Analysis of P-P-N 10T SRAM cell for IoT based devices

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Ultra low power integrated circuits got the major attention due to its lower power dissipation in the era of Internet of Things (IoT) based smarter devices. In this context, a P-P-N based 10T SRAM cell has been designed and simulated on cadence virtuoso tool with GPDK 45nm technology node at supply voltage ranges from 0.6V to 1V. The various parameters such as static noise margin, read/write power, read/write delay of the 10T SRAM cell are determined out and compared with other considered topologies. It is interesting to notice that 10T SRAM cell shows commendable improvement in read static noise margin (RSNM) i.e. 36% and 46% as compared to conventional 6T and differential 8T SRAM cells respectively. The 10T SRAM cell also has reduction in read power of 38.52% and 38% as compared to conventional 6T and differential 8T SRAM cells respectively. The read delay of P-P-N based 10T SRAM cell is improved by 40% with compared to conventional 6T SRAM cell.