Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory

Abstract

In this paper, we have proposed a novel low power Finfet based Sram cell design which has different read access path and write access path. The proposed cell achieves better performance compared to conventional sram cell. Proposed cell achieves 78% for hold 1 and 67% for hold 0 static power reduction than conventional 8T and 6T Sram cell. The proposed sram cell achieves 69% and 58% for write performance in terms of power and delay. Read delay is also reduced by approximately 89% and read power is reduced by 87%. Compared to conventional 8T Sram Cell. The proposed cell is read SNM free and has better SNM for write compared to Conventional Sram Cell.