Optimization of power and energy in FinFET based SRAM cell using adiabatic logic

Abstract

Background/Objective: In the recent years, the instantaneous power consumption and the total energy dissipation of a circuit have become very important factors to be considered in complex VLSI system design solutions. The adiabatic logic is a technique, which is used to optimize the power dissipation and the energy recovery capability of these circuits, and this logic makes the VLSI circuits reuse the consumed power. This paper compares different adiabatic SRAM cell structures presented in the literature. Furthermore, the conventional SRAM cell and all the related designs are implemented using FinFET devices aiming at low power operation capability. Methods/Statistical analysis: The SRAM cell design is carried out in Cadence® EDA environment and power and energy values are estimated for the CMOS processes, namely, 180nm and 32nm followed by the 32nm FinFET technology. The two different technology libraries have been employed to identify the effects of the lower technology nodal effect on the power dissipation. The layouts for these SRAM cells have been drawn using Cadence® Assura tool. Findings: The results show that the power consumption of the FinFET based adiabatic SRAM cells (8T and 9T cell structure) is less than the conventional 6T CMOS based SRAM cell. Conclusion/improvement: In this paper, the conventional SRAM cell and the adiabatic SRAM cells with different technology nodes, namely, DSM and UDSM are compared for their power and energy values. The adiabatic logic displays lower power and energy consumption compared to those incurred by the conventional 6T CMOS SRAM cell. Furthermore, the FinFET device based circuits portrays advantages with its better control over the device channel and reduced short channel effects, resulting in reduced leakage power. The FinFET based SRAM cell employing the adiabatic logic incurs the minimum power and energy dissipation.