Design of High Performance FinFET SRAM Cell for Write Operation

Abstract

A novel FinFET based SRAM cell is proposed to reduce the dynamic power consumption during write mode in this research work. The proposed High Performance FinFET SRAM (HPFS) cell consists of 8-Transistors instead of 6-Transistors as in conventional SRAM cell. The extra two transistors are used to reduce the write power during transition. The proposed circuit is simulated for Microwind EDA tool. The results of HPFS cell is compared with conventional SRAM cells. From the simulated results, it has been observed that the suggested HPFS cell consumes lower power and provides lower access delay compared to other cells.