45nm Node Research Articles

Placement Flow Study and Detailed Placement for Hybrid-Row-Height Designs

At the 3 nm node, a hybrid-row-height design paradigm has emerged for better power efficiency and performance optimization. A diverse cell library that includes multiple variants of a cell with different fin counts is available. Instead of using cells with the same fin count for the entire chip, a design may combine cells with two different fin counts. Cells with the same fin count can be laid down in the same row resulting in a chip with hybrid row heights. With this brand-new design paradigm, revisiting and revamping the conventional VLSI placement flow becomes necessary. There were attempts that addressed the placement problem associated with hybrid-row-height design at the global placement stage or the placement legalization stage. In this work, we first propose an effective detailed placement approach suitable for hybrid-row-height designs and then conduct a comprehensive study to evaluate the different options of forming a complete hybrid-row-height design placement flow. For the first time, the advantage of considering the row configuration early on in the global placement stage is confirmed. Besides, our proposed detailed placement approach can improve the final half-perimeter wirelength by over 7% on average which more than double the improvement obtainable by a basic detailed placement algorithm similar to the well-known FastDP.

Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters

Calibration of models and data structures is recurring in a large number of cross-cutting applications from finance to engineering. Even though there are numerous and well-established specific calibration techniques for each application sector, using Neural Networks (NNs) can improve performance. For instance, Tapped Delay-Line Time-to-Digital Converters (TDL-TDCs) implemented in Field Programmable Gate Arrays (FPGAs) are increasingly being used in a variety of research applications, such in the time-resolved spectroscopy or in medical imaging mainly for their high-precision and flexibility. Specific decoding on the sampled information from the TDL, together with calibration to compensate for non-idealities, (i.e., Bubble Errors, BEs, and Process–Voltage–Temperature fluctuations, PVTs) are carried out for generating the conversion of digital codes to time units. In this fundamental process, the impact of Machine Learning (ML) usage has not yet been investigated. In this paper, focusing on advanced FPGA devices (i.e., 28-nm, 20-nm, and 16-nm), we propose an approach based on NNs running in Python on a standalone PC to identify the optimal conversion from digital codes to timestamps, comparing it with the classical fully FPGA-based solution c literature. The experimental validations are performed on Artix-7 (XC7A100TFG256-2) and Kintex UltraScale (XCKU040-FFVA1156-2-E) in 28-nm and 20-nm technology nodes, achieving precision of 12.9 ps r.m.s. and 4.85 ps r.m.s., respectively. These results are in line with the state-of-the-art, demonstrating that in 28-nm technology, the bubble compression algorithm is sufficient to achieve high-precision, while reordering mechanism is crucial to compensate for BEs within the 16/20-nm technology node.

A Framework for Overcoming Resolution and Sensitivity Limits in 7nm Node Technology Inspection via Automated Imaging and Analysis

A Framework for Overcoming Resolution and Sensitivity Limits in 7nm Node Technology Inspection via Automated Imaging and Analysis

Advantages, manufacturing processes and challenges of FinFET technology

Abstract As an emerging cutting-edge integrated circuit technology, Fin Field Effect Transistor (FinFET) has not only successfully broken through the limitations of the 22nm node since its development in 1998, but it still maintains considerable vitality and is developing into smaller sizes. As an improvement over traditional MOSFET technology, FinFET offers many technical advantages, which practically solve the challenges encountered by traditional MOSFET. The FinFET process technology is incompatible with planar MOSFET process technology. Moreover, since the development of Finfet technology, there have been many technical challenges. The first half of this article mainly introduces the differences and advantages between FinFET and traditional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and briefly outlines its manufacturing process. The second half explains the challenges and hopes on the development path of FinFET technology. I believe this article can provide a reference for integrated circuit designers when understanding FinFET technology, and provide guidance and reference for beginners.

Challenges for Leading Edge node FINFET

The primary focus of this work is to find out the challenges associated with 7nm node finFET. To enable the current generation of gadgets/instruments, foundries are going toward smaller geometries (FinFET 7nm, 5nm, etc.) for manufacturing SOC/ASIC. To support the 7nm technology node without EUV, the Layout Design Rules have been scaled quite aggressively. As a result, obtaining satisfactory performance and yield in High Volume Manufacturing (HVM) has become a difficult undertaking. The gains in terms of power, performance, and other characteristics that become available with reduced geometries are the main drivers driving this movement. Analog/mixed-signal circuits, on the other hand, do not fully achieve these gains. They get increasingly difficult to design, with higher parasitic resistance and capacitance, more layout-dependent effects, and, in certain cases, layout growth. While in terms of fabrication the challenges are in node and cost, mask making, patterning, transistor formation, BEOL, MEOL, Technology parasitic elements and process control etc. This indicate what are the challenges for design of 7nm node FinFET.

Nanoscale single-electron box with a floating lead for quantum sensing: Modeling and device characterization

We present an in-depth analysis of a single-electron box (SEB) biased through a floating node technique that is common in charge-coupled devices. The device is analyzed and characterized in the context of single-electron charge sensing techniques for integrated silicon quantum dots (QD). The unique aspect of our SEB design is the incorporation of a metallic floating node, strategically employed for sensing and precise injection of electrons into an electrostatically formed QD. To analyze the SEB, we propose an extended multi-orbital Anderson impurity model (MOAIM), adapted to our nanoscale SEB system, that is used to predict theoretically the behavior of the SEB in the context of a charge sensing application. The validation of the model and the sensing technique has been carried out on a QD fabricated in a fully depleted silicon on insulator process (FD-SOI) on a 22-nm CMOS technology node. We demonstrate the MOAIM's efficacy in predicting the observed electronic behavior and elucidating the complex electron dynamics and correlations in the SEB. The results of our study reinforce the versatility and precision of the model in the realm of nanoelectronics and highlight the practical utility of the metallic floating node as a mechanism for charge injection and detection in integrated QDs. Finally, we identify the limitations of our model in capturing higher order effects observed in our measurements and propose future outlooks to reconcile some of these discrepancies.

Designing and performance analysis of 7 T CNTFET based novel SRAM cell for IoT application

The selection of the title includes designing of SRAM cell using CNTFET because CNTFET overcomes all the issues coming from CMOS technology beyond the 10nm technology node. With the reduction in channel length, the threshold voltage required for CMOS-based technology increases, and the corresponding off-state current decreases. This can prove to be a significant advancement for the semiconductor industry. With the evolution of the new generation of the technology era, especially beyond 10 nm, CMOS is not able to fulfil all the required conditions, as beyond 10 nm technology node, threshold voltage decreases, and consequently off-state current and leakage power increase. This is the reason that CNTFET can be considered a prominent replacement of CMOS transistor for the designing of SRAM cells with the technology node beyond 10 nm. This designed SRAM cell is applicable for IoT applications because IoT uses a microcontroller and the SRAM cell is used as a data memory in the microcontroller. A Data memory always requires high speed, ultra-low power dissipation, and high stability from the cell. Thus, to fulfil this requirement, performance analysis to identify the problem statement of conventional cells and then to improve their performance based on the findings is essential. This is the reason that the 7 T CNTFET-based SRAM novel cell is introduced, and its performance is going to be further improved so that the designed novel cell becomes compatible with IoT applications. Leakage power and stability factor are the main performance parameters to improve of SRAM cells.

FinFET Technology: Modeling and RF Characterization for 5nm Node Technology: A Review

The study offers new methods for understanding and simulating the radiofrequency, analog, and thermal characteristics of the FinFET at the 5nm CMOS technology node. The results of the thermal assessment show that changes in temperature have an effect on the threshold voltage and sub-threshold slope (SS). The maximum oscillation frequency and cut-off frequency of an n-FinFET RF device with a single gate contact are revealed by the RF investigation. Additionally, the study provides information about the device-level temperature sensitivity of the analog and RF Figures of Merit (FoMs) for the 5nm technology. The industry-standard BSIM-CMG model is adjusted to include the effects of self-heating (SH) and parasites in order to improve model accuracy. The updated BSIM-CMG model increases accuracy by taking self-heating and parasite effects into account. Effective heat pathways for lowering junction temperature are found by employing vias on silicon and stacks of conductive materials made of metal. It should be remembered, though, that using these heat pathways could raise parasitic capacitance and negatively impact the circuit's functionality. Keywords: RF Characterization, Thermal Impact, Self-Heating, Figure of Merit, FinFET, Analog Characteristics.

(Keynote) ALD Challenges and Opportunities in Light of Future Trends in Si-Based Nanoelectronics

To enable CMOS transistor density scaling following Moore’s Law, device architectures transitioned in the past decade from the historical 2D planar transistor to FINFET. The next innovation touted for the 3nm node is a 3D stacked gate-all-around architecture in combination with a backside power delivery network. For further scaling, stacking nmos and pmos, the so-called complementary-FET (CFET) design, is envisaged to happen in 2030. The shrinking device dimensions of the interconnects require also new metallization schemes to tackle the RC challenge, such as Cu replacements materials in a direct metal etch integration scheme. Beyond the CFET era, one envisages the introduction of 2D-grown channel materials that will pave the way for further scaling. A broad variety of complementary deposition techniques will be needed to enable the above-mentioned novelties; among them ALD that will play a crucial role.A similar trend towards stacking functional cells can be observed in various memories, such as the emerging memories that aim to bridge the gap between DRAM and NAND, thereby enabling fast data storage and retreival for real-time processing in connected devices at low cost. These memories are based on phase change, filamentary, magnetic, or ferroelectric mechanisms and often use multi-element materials. They have been extensively explored in 2D capacitor or transistor based devices, but for further density scaling 3D device designs are needed where a conformal deposition technique such as ALD is required. Cell scaling challenges also hold for the traditional DRAM which lead to exploring 3DDRAM integration routes. One viable pathway for scaling implies the replacement of the typical Si-channel based transistor by a deposited semiconductor oxide channel. Ultimate 3DDRAM implementation would require a conformal deposition of that channel.In this presentation, we will discuss the opportunities and challenges of ALD in a 3D-evolving device landscape where new materials will play a key role.

Domestic Advanced Packaging for Hi-Rel Microelectronics: The Future is Now

Growing interest in and proliferation of heterogeneously integrated microsystems for enhanced performance of modules and microsystems. Recent years have seen significant adoption of these technologies in commercial applications, driven by major fabless device companies and 1 1st -tier vertically integrated foundries & OSATs. 67% of semiconductor wafer production at > 40nm node (Mario Morales, IDC presentation at 2022 WLPS) → integration of legacy and leading edge device technologies to produce microsystems.

Statistical Compact Modeling With Artificial Neural Networks

This work proposes a statistical modeling approach for the artificial neural network (ANN) based compact model (CM). The method of retaining part of the network features of the nominal device and further finetuning the network parameters (variational neurons) is found to accurately reproduce the static variation. A mapping from process variation to network parameters is derived by combining the proposed variational neuron selection algorithm and the backward propagation of variance (BPV) method. In addition, a secondary classification of the selected variational neurons is applied to model the fabrication-induced correlation between n-and p-type devices. The NN-based statistical modeling approach has been well implemented and verified on the GAA simulation data and the 16nm node foundry FinFET, which indicates its great potential in modeling emerging and advanced device technology.

Thermal Crosstalk Analysis of Phase Change Memory Considering Thermoelectric Effect and Thermal Boundary Resistance

Phase change memory (PCM) has emerged as a promising memory for next-generation applications due to its high-speed read and write capabilities as well as non-volatility. However, as PCM scales down to smaller feature sizes, it faces the challenge of thermal crosstalk. During the reset operation, a large amount of heat is generated and dissipated in the PCM array, potentially affecting adjacent memory cells, compromising device stability, and limiting high-density integration. To accurately investigate the thermal crosstalk in the PCM array, the conventional finite element model of the PCM array is improved by incorporating the thermoelectric effect and thermal boundary resistance. Under the 65, 45, 32, and 22-nm process nodes, the improved model reveals the occurrence of thermal crosstalk within the PCM array, whereas the conventional model is unable to detect this phenomenon at the 65-nm node. The improved model proposed in this paper incorporates more comprehensive considerations, providing a more precise analysis of the thermal crosstalk phenomenon in the PCM array, and thereby offering theoretical reference for high-density integration of the PCM.

Design of GPIO Transmitter

Abstract: This paper presents a comprehensive design approach for a versatile 1.8V GPIO transmitter tailored for a 5pf load capacitance. The work introduces a novel design that accommodates 1.8V IO supply, enhancing the flexibility and compatibility of the GPIO transmitter. The GPIO consists of a level shifter and a driver. A level up shifter is used along with a driver capable of driving the signals without any data loss. The work embarks on the objective of designing a robust GPIO transmitter by utilizing a combination of level shifting and driver circuitry. The methodology encompasses meticulous simulation-driven design, encompassing a 45nm technology node and the Cadence Virtuoso platform. The design incorporates a level shifter that elevates input data from a core domain operating at 0.8V to IO levels of 1.8V , ensuring seamless communication across various voltage domains. The driver circuit, implemented with progressive sizing, effectively drives the substantial load capacitance of 5pF, maintaining the integrity of input data. Through detailed analysis, the architecture ensures compliance with the demanding specifications of Intel Max 10 FPGA. Simulation results exhibit the efficacy of the proposed design. The level shifter successfully transforms an incoming 0.8V data signal to 1.79V , aligning with the 1.8V IO requirements. The driver also drives the same signal out with a load of 5pf. The level shifter and driver is combined to check for the working of transmitter, with input at 0.8V and the signal is obtained at the expected voltage level at the output of driver

A Temperature Compensated Voltage Controlled Relaxation Oscillator for Frequency Modulated DC-DC Charge Pump Regulation

Relaxation oscillators with wide dynamic range are required for low power frequency modulated switch mode DCDC regulator designs. In this brief, a temperature compensation technique with variable threshold control for Voltage Controlled Relaxation Oscillator (VCRO) is presented. The voltage to current conversion circuit reduces the drift in the frequency gain across temperature by introducing a PMOS-NMOS current gain compensation scheme. The current gain circuit also allows absolute control on the minimum value of control voltage after which VCRO starts doing voltage to frequency conversion. This restricts the amplifier to go out of saturation which is inherently generating the control voltage for VCRO. Measurement results show that across temperature range of -40 oC to 150 oC, the oscillator achieves a temperature stability of 187 ppm/oC at 18MHz and 171 ppm/oC at 92.5MHz respectively. Implemented in 90nm process node, it occupies 57μm×32μm area while dissipating 2.61 nW/KHz from a 1.5V supply.

An efficient GNRFET-based circuit design of ternary half-adder

Attaining low energy consumption in digital circuits design is a main task for designers because emerging applications are based on batteries and face limited-energy. Designing digital circuits with application to multiple-valued logic (MVL) and graphene nanoribbon field-effect transistor (GNRFET) provides a huge improvement in energy consumption. In this regard, this paper presents a novel ternary Half-Adder (THA) implemented with metal-oxide semiconductor (MOS)-type GNRFET. In the proposed THA, the Sum circuit is based on a combination of 3:1 ternary multiplexer, unary operators, and two supply voltages (dual-VDD), and the Carry circuit is based on unary operators, pass-transistor logic, and dual-VDD. The proposed THA is simulated using the 32-nm MOS-type GNRFET technology node at 0.9 V supply voltage in the HSPICE simulator. The proposed THA reduces the transistors count by 5.71–26.67% compared to the previously published THA circuits available in the literature, which are similar to the proposed THA from the design approach point of view. It is concluded from the simulation results that the proposed THA improves the power and energy consumptions by 83.33–91.41% and 66.38–82.27%, respectively. Moreover, the proposed THA is also designed and simulated using the Stanford 32-nm carbon nanotube field-effect transistor (CNTFET) technology. The proposed MOS-type GNRFET-based THA reduces the power and energy consumptions by 84.79% and 68.03%, respectively, and increases the delay by 2.12 × compared to its CNTFET-based counterpart. Moreover, the proposed CNTFET-based THA offers the second-lowest delay and power and the third-lowest energy compared to other existing CNTFET-based THA circuits.

VLSI Design of Saturation-Based Image Dehazing Algorithm

Hazy weather degrades the vividness of the images captured by real-time systems for applications such as object detection, remote sensing, and surveillance systems. This affects the performance of such real-time systems. The hardware implementation of a real-time haze removal system is imperative to solve these problems. Such a solution is proposed in this article. Here, the saturation-based hardware implementation of an image dehazing system is presented. To estimate atmospheric light more precisely, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15\ttimes 15$</tex-math> </inline-formula> window minimum filter is implemented, which uses the downsampled hazy image to estimate the atmospheric light. Furthermore, we have employed saturation-based transmission map estimation, which makes our approach pixel-based rather than patch-based. Unlike existing patch-based methods, the proposed method requires neither an edge detection unit nor an image filtering unit to suppress halo artifacts around edges. The VLSI architecture of the proposed dehazing system comprises seven pipelined stages. It is implemented on FPGA as well as ASIC (65-nm technology node) platforms. The ASIC implementation of the proposed dehazing system yielded a maximum throughput of 624 Mpixels/s, which is fast enough to process <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3840\ttimes 2160$</tex-math> </inline-formula> resolution at a rate higher than 70 fps with only 13.2k logic gates count.

Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing

In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Depleted Silicon on Insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_t</i> ) to be adjustable (i.e., low-Vt and high-Vt states) by using the back gate bias. Our design utilizes the front and back gates of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like; NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like; half adder and full adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.

Performance Analysis of Deep Sub Micron Two Quadrant Analog Divider Circuits

Abstract: Current mode Analog Dividers are widely used in various circuits such as fuzzy logic controllers, neural networks, adaptive filters and variable gain amplifiers. When these current analog divider circuits implemented in DSM technology, many of the second order effects starts deteriorating its performance. Most of the available literatures on analog dividers are reporting performance of these circuits implemented using long channel MOSFETs. Hence it is a peak time to compare the performance variation between various proposed analog circuits implemented in lower technological nodes. This is for identifying most reliable circuit which safely works in this node. .In this work a comparative performance analysis of two quadrant CMOS analog divider against two quadrant CMOS approximation divider using 45nm technological node has been carried out. The obtained result indicates that Approximation Divider is reliabie than two quadrant CMOS analog divider. The entire work is carried out using Tanner software.

Design and Implementation of Low Power Time-To-Digital Converter using MGDI Technique

This paper introduces a novel Time to Digital Converter (TDC) architecture based on the Modified Gate Diffusion Input (MGDI) technique, which is derived from the well-established GDI method. Through the utilization of MGDI-based logic gates and digital circuitry, this innovative approach leads to a substantial reduction in the number of transistors required for implementation. As a result, it offers significant advantages in terms of circuit area, power consumption, and propagation delay, while simultaneously simplifying the complexity of the overall logic design. The functional blocks within the TDC have been optimized to efficiently process an internal clock frequency of 5MHz. This achievement is realized using cutting-edge 90nm MGDI technology, operating at a supply voltage of 1V. Practical implementation of this design can be carried out seamlessly with Cadence Virtuoso tools in the 90nm technology node. In essence, this research effort represents a promising advancement in the realm of time-to-digital conversion. By harnessing the capabilities of MGDI and its transistor-saving attributes, the proposed TDC not only enhances performance but also addresses critical concerns such as power efficiency and chip area utilization. These advancements make it a compelling choice for applications requiring precise time measurements, while the compatibility with contemporary technology nodes ensures its relevance and applicability in modern integrated circuit design.

IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages

The detail routing process is by far the most time consuming during the physical design flow. Routing starts with an estimation of timing slacks and aims to meet the timing specifications at signoff. In this paper, we propose an improved method to predict the net delays using RandomForestRegressor and thereby predict critical paths early on at the placement stage. Quick timing prediction is also essential in making time-sensitive edits to stepping of the chip based on post-Si feedback. The proposed algorithm is based on five novel features, namely, targeted feature selection, introduction of a one-hot encoding scheme, an outlier identification method, post-route buffer-bloat prediction, and post-route cell sizing prediction. Experimental results on academic benchmarks and industry circuits, both on advanced 10nm process node show that the proposed algorithm has led to significant improvements in accurately predicting timing slacks when compared with state of the art. The proposed algorithm predicts slack within 0.598% of signoff results, whereas the state of art results are erroneous by an average of 53.33% for the same metric. Overall time savings of 44.1% is seen when compared to running the traditional flow, and savings of 90% is seen for obtaining the timing results.