Design of GPIO Transmitter

Abstract

Abstract: This paper presents a comprehensive design approach for a versatile 1.8V GPIO transmitter tailored for a 5pf load capacitance. The work introduces a novel design that accommodates 1.8V IO supply, enhancing the flexibility and compatibility of the GPIO transmitter. The GPIO consists of a level shifter and a driver. A level up shifter is used along with a driver capable of driving the signals without any data loss. The work embarks on the objective of designing a robust GPIO transmitter by utilizing a combination of level shifting and driver circuitry. The methodology encompasses meticulous simulation-driven design, encompassing a 45nm technology node and the Cadence Virtuoso platform. The design incorporates a level shifter that elevates input data from a core domain operating at 0.8V to IO levels of 1.8V , ensuring seamless communication across various voltage domains. The driver circuit, implemented with progressive sizing, effectively drives the substantial load capacitance of 5pF, maintaining the integrity of input data. Through detailed analysis, the architecture ensures compliance with the demanding specifications of Intel Max 10 FPGA. Simulation results exhibit the efficacy of the proposed design. The level shifter successfully transforms an incoming 0.8V data signal to 1.79V , aligning with the 1.8V IO requirements. The driver also drives the same signal out with a load of 5pf. The level shifter and driver is combined to check for the working of transmitter, with input at 0.8V and the signal is obtained at the expected voltage level at the output of driver