Design of level shifter for low power applications

Abstract

The paper demonstrates a new configuration of level shifters for low power application which is a 45nm CMOS technology and simulated in cadence tool. Conventional level shifter is being designed utilizing the six transistors, eight transistors and ten transistors. The parameters being calculated for the circuit designed are average power dissipation, average noise and leakage voltage. This type of level shifter requires two different voltage supplies: the input logic signal voltage supply (VDDL) and output logic signal voltage supply (VDDH). The voltage used for the working of the designed circuits has been from 0.2 volt to 0.7 volt. Level shifter circuits are popularly used as an interface to different voltage domain in System on chip (SoC) and modern ICs. It has been known that conventional level shifter has the ability will achieve low power operation and convert high voltage digital input signals to high voltage digital output signals. A conventional level shifter capable of handling extremely low voltage input. It is used to shift any voltage level to a desired level. This level shifter fulfills those needs of lower power system and also will a useful for ICs and system on chip (SoC).