Challenges for Leading Edge node FINFET

Abstract

The primary focus of this work is to find out the challenges associated with 7nm node finFET. To enable the current generation of gadgets/instruments, foundries are going toward smaller geometries (FinFET 7nm, 5nm, etc.) for manufacturing SOC/ASIC. To support the 7nm technology node without EUV, the Layout Design Rules have been scaled quite aggressively. As a result, obtaining satisfactory performance and yield in High Volume Manufacturing (HVM) has become a difficult undertaking. The gains in terms of power, performance, and other characteristics that become available with reduced geometries are the main drivers driving this movement. Analog/mixed-signal circuits, on the other hand, do not fully achieve these gains. They get increasingly difficult to design, with higher parasitic resistance and capacitance, more layout-dependent effects, and, in certain cases, layout growth. While in terms of fabrication the challenges are in node and cost, mask making, patterning, transistor formation, BEOL, MEOL, Technology parasitic elements and process control etc. This indicate what are the challenges for design of 7nm node FinFET.