Yield and Reliability Challenges at 7nm and Below

Abstract

Layout Design Rules have been scaled very aggressively to enable the 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. Moreover, due to overlay tolerance requirements and diminishing process windows, reliability risks due to soft shorts/leakages and soft opens for both FEOL and BEOL have also increased to a critical level. Introduction of EUV at the second wave of7nm and 5nm will not help significantly due to increased defectivity and significant increases in Local Edge Roughness. New characterization techniques are necessary to identify the yield and reliability risks. After reviewing the evolution of design rules and classifying the yield and reliability risks, we will present examples f T om Design-For-Inspectio$n^{TM}$ $(DFI^{TM}$) and the novel VarScan methodology to “detect the undetectable” defects and characterize variability for both FEOL and BEOL 7nm and below technologies.