45nm Node Research Articles

Quantum Transport in 40-nm MOSFETs at Deep-Cryogenic Temperatures

In this letter, we characterize the electrical properties of commercial bulk 40-nm MOSFETs at room and deep cryogenic temperatures, with a focus on quantum information processing (QIP) applications. At 50 mK, the devices operate as classical FETs or quantum dot devices when either a high or low drain bias is applied, respectively. The operation in classical regime shows improved transconductance and subthreshold slope with respect to 300 K. In the quantum regime, all measured devices show Coulomb blockade. This is explained by the formation of quantum dots in the channel, for which a model is proposed. The variability in parameters, important for quantum computing scaling, is also quantified. Our results show that bulk 40-nm node MOSFETs can be readily used for the co-integration of cryo-CMOS classical-quantum circuits at deep cryogenic temperatures and that the variability approaches the uniformity requirements to enable shared control.

Understanding the Key Parameter Dependences Influencing the Soft-Error Susceptibility of Standard Combinational Logic

This article presents neutron radiation-induced soft error rate (SER) statistics and detailed analysis thereof, revealing a multitude of circuit parameters impacting the soft-error susceptibility of standard combinational logic in advanced CMOS nodes. A high-density array-based soft-error characterization vehicle is presented, featuring standard logic gate chains of varying lengths. Neutron irradiation data obtained from gate variants employing devices with distinct channel widths and threshold voltage flavors is analyzed at multiple supply voltages, ranging from nominal down to near-threshold. Supplemented with first-order simulations, measured SER cross-section results obtained from test structures implemented in a 65-nm planar CMOS technology node reveal the complex interplay between factors, such as supply voltage, node capacitance, restore current ( $I_{\mathrm {RESTORE}}$ ), gate topology, and logic chain length responsible in contributing toward the collective soft error susceptibility of a standard gate type, which constitutes the main focus of this article. In addition, the easy process portability of the proposed macro is demonstrated through implementation in a 16-nm FinFET process.

Performance Analysis of Non-Identical Master Slave Flip Flops at 65nm Node

This paper presents the performance analysis of the different master slave flip flop reported and comparison of their parameters such as power, area, delay setup time and hold time. To reduce the number of transistor count various logic structure mater slave design have been proposed that results reduction in total area of the flip flop. Advantage and disadvantage of the each flip flop has been discussed. Process corner analysis of all flip flop is also presented at supply voltage of 0.7 volts at 27°C temperature. Percentage reduction in power and speed of operation i.e. frequency are discussed

A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design

In this paper, a novel energy efficient 12T memory cell is proposed which is radiation hardened by design (RHD) to tolerate single-event multiple-node upsets (SEMNU) in near threshold voltage regime. The radiation hardness of the proposed memory cell is improved by controlling the cross coupled inverters’ PMOS devices through dummy access transistors. We validated the proposed memory cell in STMicroelectronics 65-nm CMOS technology. The post layout parasitic extracted simulations show that by employing the proposed RHD-12T memory cell, an average improvement of ~ 42%, 17%, 17%/9% and 6%/7% in layout area, power dissipation, read/write access time, and read/write static noise margin, respectively, is obtained over the recently reported 12T memory cell at supply voltage of 0.4V. We also validated the proposed memory cell at 32-nm CMOS technology node using technology computer-aided design (TCAD) mixed-mode simulations. In the 32-nm technology, the proposed RHD-12T memory cell shows an average improvement of ~15%, 10%/56%, and 8%/10% in power dissipation, read/write access time, and read/write static noise margin, respectively, over the 12T memory cell at supply voltage of 0.3V. Combining layout-topology, HSPICE post layout simulations and TCAD mixed mode simulation results clearly show that the proposed memory cell effectively tolerates single event upset as well as SEMNU. In 32nm technology our memory cell can provide SEMNU tolerance up to the value of LET equals to 62 Mev-cm2/mg.

On the Cross-Correlation Based Loop Gain Adaptation for Bang-Bang CDRs

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to jitter noise, previous works exploit the autocorrelation function at the output of the bang-bang phase detector as a proper indicator to track the system dynamics and perform loop gain adaptation. In contrast, we propose the XCALG as a new alternative to perform loop gain adaptation featuring better observability, less impact from jitter sources while keeping a safe phase margin. Theory behind the idea is enhanced, and the XCALG is demonstrated through behavioral system simulations. In addition, preliminary implementation costs of the cross-correlation function are discussed using a 65nm CMOS technology node.

Impacts of Process and Temperature Variations on the Crosstalk Effects in Sub-10 nm Multilayer Graphene Nanoribbon Interconnects

In this study, a comprehensive analysis of the crosstalk in multilayer graphene nanoribbon (MLGNR) interconnects in the presence of process and temperature variations is performed. The variations of the crosstalk delay, crosstalk noise area, and power are investigated in the presence of process and temperature variations for passively shielded five-line MLGNRs carrying ternary signals in 10nm and 7nm technology nodes. Analyses are conducted considering all of the important sources of process variations using comprehensive Monte Carlo simulations. The results indicate that the impacts of the process and temperature variations on the crosstalk effects become more evident with the technology scaling from 10 to 7nm, mainly due to the reduction of the width and spacing of the interconnects. According to the results, the maximum deviation of the crosstalk delay, power consumption, and noise area are 160ps, $0.9{\mu }\text{W}$ and 16V.ps, respectively for 10nm passively shielded MLGNR interconnect in the presence of all sources of process variations. These values are in turn 335ps, $1.3{\mu }\text{W}$ , and 27V.ps in 7nm node. Moreover, the crosstalk effects are evaluated at various temperatures ranging from 200°K to 450°K. The maximum variations for the crosstalk delay and noise area for 10nm MLGNR interconnects are 57ps and 6V.ps at temperatures higher than room temperature and 6ps and 0.5V.ps for temperatures lower than the room temperature. These variations are in turn 118ps, 9V.ps, 12ps and 1V.ps for 7nm MLGNR interconnects. It is also observed that the variations of the resistance of the $500{\mu }\text{m}$ length MLGNR in the presence of temperature variations are on average 3.9 $\text{K}\Omega $ and 8.2 $\text{K}\Omega $ in 10nm and 7nm technologies, respectively.

Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Containing Boron-10

Single-event upsets (SEUs) were measured in thermal neutron-irradiated microcontrollers with 65- and 130-nm-node static random-access memories (SRAMs). The suspected upset mechanism is charge deposition from the energetic byproducts of 10B thermal neutron capture. Although elemental analysis confirmed that both microcontrollers contain 10B, only the 65-nm node microcontroller exhibited a strong response to thermal neutrons. Monte Carlo simulations were performed to investigate the effects of 11B enrichment on thermal neutron-induced SEUs in a 65-nm SRAM node when boron is present in the p -type well, p -type source and drain, or tungsten plug. Simulations indicate that the byproducts of 10B(n, $\alpha $ ) 7Li reactions are capable of generating sufficient charge to upset a 65-nm SRAM. The highest amount of charge deposition from 10B(n, $\alpha $ ) 7Li reaction byproducts occurs when natural boron is used to dope the p -type source and drain regions. Simulations also show that the SEU cross section is nonnegligible when 11B-enriched boron is used for doping.

ULPAC: A Miniaturized Ultralow-Power Atomic Clock

This article introduces a chip-scale ultralow-power atomic clock (ULPAC) in the microwave frequency region. A new suspended quantum package architecture along with a fully integrated frequency probing and locking loop implemented in CMOS technology results in a compact package and ultralow-power consumption. In addition, dedicated low-noise magnetic field and temperature control loops are incorporated for isolating and mitigating the internal and external factors affecting the frequency stability. The output frequency of a crystal oscillator is continuously compensated and stabilized by locking to the peak of a coherent population trapping signal, thereby inheriting the superior frequency stability of the atomic resonance. The proposed ULPAC system achieves a frequency stability of $2.2 \times 10^{-12}$ at an averaging time of 105 s, while consuming 59.9 mW. The frequency probing and locking circuits implemented in a standard 65-nm CMOS process node occupy an area of 2.55 mm2. The prototype of this atomic clock occupies a volume of 15 cm3.

A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees

To trigger events for application-specific data transfer among registers in a multimillion-gate system-on-chip (SoC), various kinds of clock signals, selectively driven by different frequency-dependent sources and/or dividers (DIVs), are usually centralized in one or more clock generation modules, where clock gating cells (CGCs), multiplexers (MUXes) and DIVs are used to create the clocks required by different functional operations in an SoC. These modules will introduce uncommon and longer timing paths for clock propagations and further make the clock tree synthesis (CTS) process become more challenging due to the on-chip-variation (OCV) effects. In addition, high volume of switching activities in the increased number of clock logic cells will consume more power. In this article, a novel design platform, merging and replacing of multiple multiplexers and dividers (MRMMD), is developed to intelligently identify those suspicious clock architectures and resynthesize them into a power-and-area effective and less complicated clock structure. Using our resynthesis platform, not only the number of clock-related timing paths and their corresponding logic levels can be reduced, but also the corresponding analysis and implementations of clock skew minimizations during CTS become much easier. The experimental results implemented in TSMC 55- and 28-nm process nodes on optimizing some industrial clock architectures showed that significant reductions of area, power, latency, skew and clock path, logic level, OCV impact, total wire length, and implementation runtime are achieved using our MRMMD platform.

AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed

In this article, we present innovative microarchitectural designs for multilayer deep neural networks (DNNs) implemented in crossbar arrays of analog memories. Data is transferred in a fully parallel manner between arrays without explicit analog-to-digital converters. Design ideas including source follower-based readout, array segmentation, and transmit-by-duration are adopted to improve the circuit efficiency. The execution energy and throughput, for both DNN training and inference, are analyzed quantitatively using circuit simulations of a full CMOS design in the 90-nm technology node. We find that our current design could achieve up to 12–14 TOPs/s/W energy efficiency for training, while a projected scaled design could achieve up to 250 TOPs/s/W. Key challenges in realizing analog AI systems are discussed.

Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects

We investigate the performance and reliability characteristics of Cu interconnects with Ta-based barrier layers and Co wetting layers at 7nm node dimensions with a focus on the impacts of reducing the Co thickness from 30A down to 10A. We demonstrate that while reducing Co liner thickness significantly reduces RC delay, there is a significant reduction in electromigration reliability below a thickness of 20A if used in conjunction with a PVD (physical vapor deposition) TaN barrier. However, if the PVD treatment is followed by deposition of a thin ALD (atomic layer deposition) TaN, the Co layer thickness can be scaled down to 10A without any penalty in either electromigration or time dependent dielectric breakdown (TDDB.) The combined PVD/ALD process with 10A Co enables a 14% reduction in RC delay relative to our control split.

Impact of Process Variations on Delay in Carbon Nanotube Based Bus Interconnects At Different Technology Nodes

This paper presents the impact of process variations in carbon nanotube based advanced bus interconnects such as single walled carbon nanotube (SWCNT), multi walled carbon nanotube (MWCNT) and mixed carbon nanotube bundle (MCB). The impact of temperature variations on paracitics of interconnects for variable interconnects at different technology nodes is analyzed. From the analysis, it reveal that the mixed bundle carbon nanotube offering the lower paracitics even higher temperatures compared to SWCNT and MWCNT which leads to lower delay and crosstalk effect when it is used in bus interconnects. Further we have also done delay analysis by changing the bundle area, number of shells and metallic ratio of three interconnect structures with the insertion of obtained parasitics using empirical formulas. It is proven that the mixed CNT (MCB) interconnect structures offered a lesser delay compared to other CNT interconnect structures. All the analysis has been done using MATLAB at 22nm and 32nm technology nodes.

A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design

This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a subthreshold/near-threshold regime. The proposed latch provides the TNU tolerance using two restorer circuits (RCs) to hold the correct state and a three-input clocked combinational majority circuit (CMC). The $RC$ is based on pull-up and pull-down paths, controlled by different susceptible nodes, results in better radiation hardness. We validated the proposed latch in the STMicroelectronics 65-nm CMOS technology. The postlayout parasitic extracted simulations show that, by employing the proposed latch, an average improvement of ~42% in an area-energy-delay product (AEDP) is obtained over the recently reported TNU-hardened latch (TNUHL) at a supply voltage of 0.4 V. We also validated the proposed TNUHL in a 32-nm CMOS technology node using technology computer-aided-design (TCAD) mixed-mode simulations. In the 32-nm technology, our latch can provide a TNU tolerance up to a value of linear energy transfer (LET) equal to 190 Mev-cm2/mg. The HSPICE postlayout simulations and the TCAD mixed-mode simulation results clearly show that the proposed latch effectively tolerates TNU.

Resource Shared Galois Field Computation for Energy Efficient AES/CRC in IoT Applications.

End-to-end encryption and reliability of the transmitted data are essential requirements in the present era of internet enabled smart devices. Adhering to current industry standards, the Advanced Encryption Standard (AES) and Cyclic Redundancy Check (CRC) are the two most utilized methods for ensuring security and reliability. To integrate AES and CRC functionality in ultralow-power embedded System on Chips (SoCs), dedicated computation engines/co-processors are often used, consuming valuable silicon area and additional battery power. This paper presents the design of an energy-efficient multipurpose encryption engine capable of processing both AES and CRC algorithms using a shared Galois Field Computation Unit (GFCU). By decomposing the necessary Galois Field operations of AES and CRC to their fundamental binary steps, it was possible to identify shared operations in these two algorithms. This approach allowed the development of a resource shared system architecture capable of computing AES-128 and CRC-32 using a single computation unit. The GFCU based design was implemented in an area of 151μm x 151μm in 90nm technology node. The energy consumption of the design operating at 0.8 V supply voltage for a 25.6 Mbps throughput was less than 280pJ and 140pJ for AES-128 encryption and CRC-32, respectively.

Cu pillar bump development for 7nm Chip package interaction (CPI) technology

Abstract Power, performance, and area gains are important metrics driving the CMOS technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of I/Os, and the scaling driven small IP block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14nm/16nm nodes which used 150um bump pitch coming out of a die, for 7nm node the industry is targeting 130um bump pitch for high performance devices. With this pitch reduction, conventional SnAg solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in High Performance Computing, the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of ELK cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where CTE mismatch between silicon and laminate substrate magnifies the stress. The present paper discusses successful development of Cu pillar bumps for 7nm technology. The development program included a 2-step development path. In the first step, extensive thermo-mechanical modeling was done to find optimal design of copper pillar bump for robustness of interactions with 7nm BEOL ELK layers. In the second step, a 460 mm2 7nm Silicon test Vehicle was fabricated and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7nm silicon. As a result of this development, copper pillar technology has been qualified on AMD products. Today, copper pillar is a fully integral part of AMD's ever-growing 7nm product offering in High Performance Computing.

Modeling and Evaluating the Gate Length Dependence of BTI

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

Supervised Machine Learning for Training a Neural Network as 5:2 Compressor

Machine Learning has achieved substantial development in numerous applications like image processing, pattern recognition, approximate computing etc. This paper interlinks supervised machine learning algorithm and VLSI architectures to train a neural network as exact and approximate 5:2 compressors. Probabilistic pruning type of approximation technique has been employed on the exact 5:2 compressor. This approximation technique on compressors reduces the power consumption with variation in the outputs without affecting the error limit. The simulation of 5:2 compressors and training of neural network using machine learning algorithm has been done using Spectre simulator of Cadence Design Systems at 45nm CMOS technology node and Keras library with TensorFlow background respectively.

Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications

Accurate, low-latency, and energy-efficient optical flow estimation is a fundamental kernel function to enable several real-time vision applications on mobile platforms. This paper presents neighbor-guided semi-global matching (NG-fSGM), a new low-complexity optical flow algorithm tailored for low-power mobile applications. NG-fSGM obtains high accuracy optical flow by aggregating local matching costs over a semi-global region, successfully resolving local ambiguity in texture-less and occluded regions. The proposed NG-fSGM aggressively prunes the search space based on neighboring pixels’ information to significantly lower the algorithm complexity from the original fSGM. As a result, NG-fSGM achieves $17.9{\times}$ reduction in the number of computations and $8.37{\times}$ reduction in memory space compared to the original fSGM without compromising its algorithm accuracy. A multicore architecture for NG-fSGM is implemented in hardware to quantify algorithm complexity and power consumption. The proposed architecture realizes NG-fSGM with overlapping blocks processed in parallel to enhance throughput and to lower power consumption. The eight-core architecture achieves 20 M pixel/s (66 frames/s for VGA) throughput with 9.6 mm2 area at 679.2-mW power consumption in 28-nm node.

Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance

Ternary content-addressable memory (TCAM) is a type of associative memory used in many applications for high-speed data searching. We present herein a gate-all-around (GAA) carbon nanotube field-effect transistor (CNTFET)-based self-controlled TCAM cell design with a precharge-free match line. We compare the power–delay product (PDP) and static noise margin between the GAA-CNTFET-based traditional and proposed TCAM cell designs at the 11-nm technology node with a supply voltage of 0.8 V. The simulations are performed using the Virtuoso tool for different parameter values with the Stanford University GAA-CNTFET model. The simulation results show that, compared with the traditional design, the proposed design exhibits a significant reduction in power by 51.30%, delay by 17.16%, and PDP by 59.66% for a chiral vector of (20, 16, 0) with two channels. It is observed that the best chirality for the proposed design is (14, 20, 0) for a single channel, but (16, 16, 0) and (20, 16, 0) for a dual channel in terms of power, delay, stability, and PDP.

MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization

Although recent advances in resistive random access memory (ReRAM)-based accelerator designs for deep convolutional neural networks (CNNs) offer energy-efficiency improvements over CMOS-based accelerators, they have a large number of energy consuming data transactions. In this paper, we propose MAX2, a multi-tile ReRAM accelerator framework for supporting multiple CNN topologies, that maximizes on-chip data reuse and reduces on-chip bandwidth to minimize energy consumption due to data movement. Building upon the fact that a large filter can be built with a stack of smaller ( $3\times 3$ ) filters, we design every tile with nine processing elements (PEs). Each PE consists of multiple ReRAM subarrays to compute the dot product. The PEs operate in a systolic fashion, thereby maximizing input feature map reuse and minimizing interconnection cost. MAX2 chooses the data size granularity in the systolic array in conjunction with weight duplication to achieve very high area utilization without requiring additional peripheral circuits. We provide a detailed energy and area breakdown of each component at the PE level, tile level, and system level. The system-level evaluation in 32-nm node on several VGG-network benchmarks shows that the MAX2 can improve computation efficiency (TOPs/s/mm2) by $2.5\times $ and energy efficiency (TOPs/s/W) by $5.2\times $ compared with a state-of-the-art ReRAM-based accelerator.