Modeling and Evaluating the Gate Length Dependence of BTI

Abstract

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.