A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design

Abstract

In this paper, a novel energy efficient 12T memory cell is proposed which is radiation hardened by design (RHD) to tolerate single-event multiple-node upsets (SEMNU) in near threshold voltage regime. The radiation hardness of the proposed memory cell is improved by controlling the cross coupled inverters’ PMOS devices through dummy access transistors. We validated the proposed memory cell in STMicroelectronics 65-nm CMOS technology. The post layout parasitic extracted simulations show that by employing the proposed RHD-12T memory cell, an average improvement of ~ 42%, 17%, 17%/9% and 6%/7% in layout area, power dissipation, read/write access time, and read/write static noise margin, respectively, is obtained over the recently reported 12T memory cell at supply voltage of 0.4V. We also validated the proposed memory cell at 32-nm CMOS technology node using technology computer-aided design (TCAD) mixed-mode simulations. In the 32-nm technology, the proposed RHD-12T memory cell shows an average improvement of ~15%, 10%/56%, and 8%/10% in power dissipation, read/write access time, and read/write static noise margin, respectively, over the 12T memory cell at supply voltage of 0.3V. Combining layout-topology, HSPICE post layout simulations and TCAD mixed mode simulation results clearly show that the proposed memory cell effectively tolerates single event upset as well as SEMNU. In 32nm technology our memory cell can provide SEMNU tolerance up to the value of LET equals to 62 Mev-cm2/mg.