Abstract

To enable CMOS transistor density scaling following Moore’s Law, device architectures transitioned in the past decade from the historical 2D planar transistor to FINFET. The next innovation touted for the 3nm node is a 3D stacked gate-all-around architecture in combination with a backside power delivery network. For further scaling, stacking nmos and pmos, the so-called complementary-FET (CFET) design, is envisaged to happen in 2030. The shrinking device dimensions of the interconnects require also new metallization schemes to tackle the RC challenge, such as Cu replacements materials in a direct metal etch integration scheme. Beyond the CFET era, one envisages the introduction of 2D-grown channel materials that will pave the way for further scaling. A broad variety of complementary deposition techniques will be needed to enable the above-mentioned novelties; among them ALD that will play a crucial role.A similar trend towards stacking functional cells can be observed in various memories, such as the emerging memories that aim to bridge the gap between DRAM and NAND, thereby enabling fast data storage and retreival for real-time processing in connected devices at low cost. These memories are based on phase change, filamentary, magnetic, or ferroelectric mechanisms and often use multi-element materials. They have been extensively explored in 2D capacitor or transistor based devices, but for further density scaling 3D device designs are needed where a conformal deposition technique such as ALD is required. Cell scaling challenges also hold for the traditional DRAM which lead to exploring 3DDRAM integration routes. One viable pathway for scaling implies the replacement of the typical Si-channel based transistor by a deposited semiconductor oxide channel. Ultimate 3DDRAM implementation would require a conformal deposition of that channel.In this presentation, we will discuss the opportunities and challenges of ALD in a 3D-evolving device landscape where new materials will play a key role.

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