Voltage Intercept Point Research Articles

Band gap and gate dielectric engineered novel Si0.9Ge0.1/InAs junctionless TFET for RFIC applications

In this study, we present a dual dielectric material gated novel Si0.9Ge0.1/InAs hetero-structure Junctionless TFET (DMG-HJLTFET), in which first time, a novel amalgamation of Si0.9Ge0.1/InAs along with HfO2 and SiO2 is used on the basis of band gap and gate dielectric engineering respectively. Our main goal is to examine the performance of the reported device in terms of radio frequency (RF), linearity, and intermodulation distortion parameters. The reported device’s (DMG-HJLTFET) result is compared with latest published articles and conventional Si-JLTFET to show the improvement. Our simulation results reveal that DMG-HJLTFET outperforms Si-JLTFET in several key metrics, such as parasitic capacitance (Cgg, 49% ↓), maximum oscillation frequency (fmax, 589 times ↑), gain bandwidth product (GBP, 238.5 times ↑), intrinsic gain (Av, 2.24 × 102 times ↑), peak transconductance (gm, 110 times ↑), and second-order voltage intercept point (VIP2, 330.2% ↑). Our findings lead us to the conclusion that DMG-HJLTFET might be a promising substitute for low-power and high-frequency applications.

Linearity and intermodulation distortion analysis of single and dual metal gate junctionless transistor

Linearity and intermodulation distortion are very crucial parameters for RFICs design. Therefore, in this work, a detailed comparative analysis on linearity and intermodulation distortion of single metal (SMG) and double metal (DMG) double gate junction less transistor (JLT) is done using TCAD silvaco suite. Furthermore, the effects of temperature fluctuation, gate length variation, and gate material engineering on the linearity performance of both devices are also studied. A few significant figures of merit, including Voltage Intercept Point 2 (VIP2), Voltage Intercept Point 3 (VIP3), Third Order Intercept Power (IIP3), 1 dB Compression Point (P1dB), Third Order Intermodulation Distortion (IMD3), and the transconductance derivative parameters First Order Transconductance (gm1), Second Order Transconductance (gm2), and Third Order Transconductance (gm3) are used to assess the device linearity and intermodulation distortion of SMG and DMG JLT's. The findings show that higher VIP2, VIP3, IIP3, 1-dB compression point and lower gm3, IMD3 values are obtained for the SMG JLT device when compared to its counterpart DMG JLT. SMG JLT, which assures strong linearity and low distortion.

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis

This study investigates the effects of temperature on RF/Analog and linearity parameters using a 3 nm technology node Step-Negative capacitance FinFET (SNC-FinFET) for the first time. The SNC-FinFET exhibits superior performance compared to the conventional step architecture, with an enhancement of 7.2% in ION (ON-current), 73.58% in IOFF (OFF-current), excellent SS (Sub-threshold Swing) of 57.51 mV/decade, and a barrier rising of 52.38%. This is due to prior DC analysis that led to the extraction of the electrical parameters such as ION, IOFF, SS and threshold voltage (VT). After that, dimensional analysis is being done in terms of gate length (LG), fin widths (Wfin1 and Wfin2), and fin heights (Hfin1 and Hfin2). The optimized dimensions for this study are LG = 18 nm, Wfin1 = 5 nm, Wfin2 = 3 nm, Hfin1 = 50 nm, and Hfin2 = 14 nm. From this point on, using the same SNC-FinFET with the optimized dimension, varying the temperature from 250 K to 400 K, degrades the RF/analog characteristics while exhibiting the opposite trend for linearity, with improvements of 40.36%, 67.42%, 49.59%, and 62.31% in the 2nd order harmonic, 3rd order harmonic, 2nd order Voltage Intercept Point, and 3rd order Voltage Intercept Point, respectively. The proposed device performance is also analyzed at the circuit level followed by noise margin calculation where at T = 400 K 46.36% of improvement in noise margin is encountered.

High-Frequency Performance Characteristics of the Double-Gate Schottky Barrier Tunnel Field Effect Transistor in Analog and Radio-Frequency Applications

In this paper, a novel structure of Double Gate Schottky Barrier Tunnel Field Effect Transistor (DG-SBTFET) has been designed and simulated. The DG-SBTFET has two sources (NiSi) and two gate metals with an HfO2. Silvaco-TCAD simulator has been used for investigating the analog and radio frequency performance of the DG-SBTFET. The proposed device (DG-SBTFET) is compared with the conventional devices in terms of electrical parameters including ION current, ION/IOFF ratio, RF performance including transconductances (gm), cut-off frequency (f T ), transit time (r), gain bandwidth product (GBP), transconductance generation factor (TGF), and transconductance frequency product (TFP). Further, we simulate the linearity characteristics of the DG-SBTFET device is compared it with other conventional devices, including the second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), and third-order input intercept point (IIP3). Hence, the proposed device (DG- SBTFET) is suitable for low-power and high-frequency applications.

DFT based atomic modeling and Analog/RF analysis of ferroelectric HfO2 based improved FET device

In this study, we systematically investigated the Analog/RF and linearity parameter of SM DGNCFET (single metal double gate negative capacitance field effect transistor) and DM DGNCFET (double metal double gate negative capacitance Field effect transistor) with the help of Cogenda Visual TCAD simulator, and also demonstrated the enhancement in the electronic and optical properties of Si-doping bulk structure by using the Quantum ATK. The analog parameters are enhanced for SM DGNCFET such better performance of switching ratio 279 times better, DIBL 54% lower, SS decay, and some other improved parameter transconductance, TGF and Radio frequency parameter is also enhanced, transconductance frequency product (TFP) for improving reliability and stability of device. Linearity parameters like that second and third order transconductance (gm2, g m3), voltage intercept point for 2nd, 3rd. Tran Blaha modified Becke Johnson (TB-mBJ) approxiamation gives the accurate band gap of crystal. In DFT based atomic study, 12.5% of Si doping in bulk structure reveals better results for ferroelectric HfO2 based crystal in the direct band gap of bandstructure is zero, Density of state (DOS) is also improved conductivity for Si doping crystal. Hence, Si doping in crystal structure is also better for conductivity.

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

AbstractThis study's objectives are to deliver a relative analysis of non‐uniformly doped (NUD) and uniformly doped Dual Metal High‐K Schottky nanowire FET (DM‐HK‐SNWFET). Surface potential, subthreshold current, subthreshold swing, and drain current have been expressed and analyzed by resolving 2D Poisson's equation with suitable boundary conditions. The analog performance of the device is verified by examining cut‐off frequency (fT), trans‐conductance frequency product (TFP), gain frequency product (GFP), and gain trans‐conductance frequency product (GTFP). The results show suitable RF circuit parameters with a high switching ratio (≈3 × 109) and low subthreshold swing (61 mV/decade) for NUD‐DM‐HK‐SNWFET. Additionally, linearity frequency of merits (FOMs) and distortion performance are also studied by numerically calculating higher order voltage and current intercept point (VIP2,VIP3, IIP3, IMD3); 1‐dB compression point and Harmonics distortions (HD2 and HD3) using transconductance (gm1) along with its higher derivativesgm2andgm3. These parameters exhibit high‐level linearity and low‐level distortion at zero crossover points in NUD‐DM‐HK‐SNWFET, making it a better contender for low‐power and high‐performance applications.

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

The variation of the temperature-dependent performance of an electronic device is one of the major concerns in predicting the actual electrical characteristics of the device as the bandgap of semiconducting material varies with temperature. Therefore, in this article, we investigate impact of temperature variations ranging from 300 to 450K on the DC, analog/ radio frequency, and linearity performance of dual material stack gate oxide-source dielectric pocket-tunnel-field-effect transistor (DMSGO-SDP-TFET). In this regard, a technology computer-aided design simulator is used to analyze DC, and analog/radio-frequency performance parameters, such as carrier concentration, energy band variation, band-to-band tunneling rate, $$I_\mathrm{DS}-V_\mathrm{GS}$$ characteristics, transconductance ( $$g_{m}$$ ), cut off frequency ( $$f_{T}$$ ), gain-bandwidth product, maximum oscillating frequency ( $$f_{\max }$$ ), transconductance frequency product, and transit time ( $$\tau $$ ) considering the impact of temperature variations. Furthermore, linearity parameters, such as third-order transconductance ( $$g_{m3}$$ ), third-order voltage intercept point (VIP3), third-order input-interception point (IIP3), and intermodulation distortion (IMD3) are also analyzed with temperature variations as these performance parameters are significant for linear and analog/radio-frequency applications. Moreover, the performance of the proposed DMSGO-SDP-TFET is compared with the conventional dual-material stack gate oxide-tunnel-field-effect transistor (DMSGO-TFET). From the comparative analysis, in terms of percentage per kelvin, the DMSGO-SDP-TFET demonstrates lesser sensitivity towards temperature variation. Hence, the proposed DMSGO-SDP-TFET is a suitable candidate for low-power switching, and biosensing applications at elevated temperatures as compared to conventional DMSGO-TFETs.

Overlapped Gate-Source/Drain H-shaped TFET: Proposal, Design and Linearity Analysis

In this paper, the proposed design of H-shaped TFET has been discussed. This design is providing a high Ion/Ioff ratio with a better Ion. HfO2 is used for better tunnelling current. The controllability of gate voltage on the drain current improves as the gate area increases. We can obtain better outcomes for current in this design by altering the architecture. With this device, Different parameters such as unit parameter, analog parameter, and linearity parameter have been studied and investigated the output of the H-TFET. As unit parameters, the electric field, electric potential, energy band diagram, and non-local band-to-band tunnelling rate (BTBT) have all been observed. Second and third-order harmonics distortion (HD2, HD3), third-order current intercept point (IIP3), third-order intermodulation distortions (IMD3), and second and third-order voltage intercept point (VIP2, VIP3) are evaluated as linearity parameters that characterize the device’s distortions and linearity. We obtained Ion\({\text{=1.6x}10}^{-4}\) A/μm,Ioff=2.1\({\text{x}10}^{-19}\) A/μm, Ion/Ioff=7.6\({\text{x}10}^{14}\),threshold voltage Vt=0.3449 V. © 2017 ElsevierInc.Allrightsreserved.

Dependence of Lateral Straggle Parameter on DC, RF/Analog, and Linearity Performance in SOI FinFET

FinFET provide themselves as a strong candidate for low-power applications. However, the enactment of a device depends upon the precision of fabrication process. The ion implantation technique of source/drain region extends towards the channel region and affects the device performance. In this paper, the DC and short channel performances like transfer characteristic, output characteristic, Subthreshold Swing (SS), threshold voltage (V T), and current ratio (I on/I off) of SOI FinFET are reported for the variation in lateral straggle parameter (σ) from 0 to 5 nm. The effect of lateral straggle on various RF/analog figure of merits (FOMs) like transconductance (g m), output conductance (g d), intrinsic gain (g m/g d), gate capacitance (C gg), cut off frequency (f c), and gain frequency product (GFP) are presented for SOI FinFET. Furthermore, the linearity performance such as higher-order harmonics (g m2, g m3), voltage intercept point (VIP2, VIP3), input intercept point (IIP3), intermodulation distortion (IMD3), and 1-dB compression point are investigated by varying the lateral straggle from 0 to 5 nm. Results reveal that ION = 0.526 mA, g m = 0.507 mS, and f c = 3 THz are obtained at σ = 5 nm, whereas, VIP2 = 27.5 V and VIP3 = 20.2 V are observed at σ = 0 nm.

Performance enhancement of charge plasma-based junctionless TFET (JL-TFET) using stimulated n-pocket and heterogeneous gate dielectric

Junctionless tunneling field-effect transistor (JL-TFET) is an excellent potential alternative to conventional MOSFET and TFET due to the lack of a steep doping profile, which makes it easier to fabricate. JL-TFET not only offers a lower subthreshold swing (SS) compared to MOSFET, but mitigates the low on-current problem associated with conventional TFET. The DC and analog characteristics of JL-TFET can be further improved by design modifications. In this research, we have presented two novel structures of JL-TFET: stimulated n-pocket JL-TFET (SNPJL-TFET) and SNPJL-TFET with heterogeneous gate dielectric. The performance of these devices has been gauged against conventional JL-TFET. Both novel structures exhibit excellent performance including point SS around 20 mV/dec, high I ON/I OFF in the order of 1014 and lower threshold voltage (V T). By analyzing RF and linearity parameters such as the transconductance generation factor, F T, transit time, total factor productivity, second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and third-order intermodulation distortion, it is observed that the proposed devices are more suitable for RF applications since they show superiority in most of the analyzed parameters.

Insights into temperature influence on analog/RF and linearity performance of a Si/Ge heterojunction asymmetric double gate dopingless TFET

The charge-plasma based dopingless (DL) tunnel field effect transistor (TFET) is considered as an emerging TFET structure resulting from its immunity against random dopant fluctuations and not requiring high thermal budgets and expensive annealing methods for fabrication. But, temperature sensitivity is a major concern to predict the reliability of a device as the bandgap of semiconductor material changes under the influence of temperature variations when used in a system. Therefore, in this manuscript, the effect of variations in temperature (200–500 K) are investigated on the analog/RF and linearity characteristics of a Si/Ge hetero-junction (HJ) asymmetric double gate (ADG) DLTFET and abbreviated as HJ-ADG-DLTFET in the entire manuscript. In this context, Silvaco ATLAS simulator is used to evaluate DC and Analog/RF performance parameters such as $$I_{D}-V_{G}$$ characteristics, transconductance ( $$g_{m}$$ ), cut off frequency ( $$f_{T}$$ ) and transconductance generation factor (TGF) considering effect of temperature variations. Furthermore, linearity parameters such as second- and third-order voltage intercept point ( $$\mathrm{VIP}_{2}, \mathrm{VIP}_{3}$$ ), 1-dB compression point, third-order input-interception point ( $$\mathrm{IIP}_{3}$$ ) and intermodulation distortion $$(\mathrm{IMD}_{3})$$ are also evaluated considering temperature variations as these FoM are significant for linear and analog/RF applications.

Linearity Performance and Distortion Analysis of Carbon Nanotube Tunneling FET

In this research work, we have varied several parameters of a carbon nanotube based tunneling field effect transistor (CNT-TFET) such as the dielectric constant of the gate insulator (κ), channel length, oxide thickness, doping level, and the nature of doping to investigate how the performance of the CNT-TFET is affected. The performance analysis has been done based on the following performance criteria: Subthreshold swing (SS), threshold voltage (VT), and on-current to off-current ratio (Ion/Ioff). In addition, we have also analyzed how linearity and distortion figures of merit such as second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3) are affected by parametric variation. By observing the impact of parametric variation on this large number of performance metrics, a compromise choice of structural parameters is possible depending on the application. Moreover, we have proposed an asymmetric doping design that suppresses the highly undesirable ambipolar behavior in CNT-TFET. In a real-space approach, the simulation study has been carried out using the elegant non-equilibrium Green’s function (NEGF) formalism considering tight-binding Hamiltonian.

Linearity Parameters Evaluation due to Lateral Straggle in Ge-Source DMDG-TFET

TFET is very favourable device than MOSFET in terms of low power design and applications. The accurate fabrication of device results in satisfactory electrical characteristics. The diffusion of source/drain regions through the ion implantation technique, extent to the channel section, which eventually changes the behaviour of device. In this letter, the linearity behaviour of Ge-source dual material double gate (DMDG) TFET is highlighted for the variation in lateral straggle parameter (σ) from 0 to 5 nm. The linearity parameters such as higher order harmonics (gm2 and gm3), voltage intercept point (VIP2 and VIP3), input intercept power (IIP3), intermodulation distortion (IMD3), and 1-dB compression point are studied in Ge-source DMDG-TFET taking σ as parameter.

Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

The paper presents the investigation of linearity distortion analysis of double gate junctionless transistor with high-k gate dielectrics and gate metals. As double gate junctionless transistors have shown high performance in digital circuits, linearity analysis is carried out to understand nonlinear behavior of the device for RFIC applications. In order to ensure minimum intermodulation and higher order harmonics at the system output, different linearity parameters like Second Order Voltage Intercept Point, Third Order distortion, Third Order Input Intercept Point and Third Order Intermodulation Distortion are evaluated. The results show that junctionless transistor should be biased at appropriate low voltage to ensure better linearity which is desired for RFICs. The effects of high-k gate dielectrics and gate metals on linearity characteristics of junctionless transistor are also investigated. Deterioration of the linearity is observed in junctionless transistor for the use of high-k insulators as gate dielectrics. It is also observed that low work function gate material is suitable to achieve higher linearity in low power applications.

The improved RF/stability and linearity performance of the ultrathin-body Gaussian-doped junctionless FinFET

The Gaussian-doped junctionless FinFET (GD-JLFinFET) is investigated for radiofrequency (RF)/analog applications. The performance of the device is analyzed by computing the transconductance (gm), transconductance-to-drain current ratio (gm/Ids), cutoff frequency (fT), and maximum oscillation frequency (fmax). The stability factor (K) is analyzed based on the Y-parameters, and the linearity of the proposed device is studied based on the gm3, second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order intermodulation intercept point (IIP3), third-order intermodulation distortion (IMD3), and 1-dB compression point. The impact of device geometrical parameters such as the fin width, fin height, channel length, voltage biases, and temperature on the RF/stability characteristics is also studied. The proposed device exhibits fT = 2.96 THz and fmax = 9.13 THz, compared with the values of fT = 0.97 THz and fmax = 5.88 THz for the uniformly doped junctionless FinFET (UD-JLFinFET). It is observed that proposed device exhibits better RF/analog characteristics.

Impact of lateral straggle on linearity performance in gate-modulated (GM) TFET

Tunnel field effect transistor (TFET) is considered as a more viable device than MOSFET for low power applications. However, the performance of any device depends on the accuracy of the fabrication process. At the time of fabrication, the ion implantation technique extends the source/drain region toward the channel which affects the device performance. In this paper, we have highlighted the linearity performance of gate-modulated TFET (GM-TFET) by varying the lateral straggle parameter (σ) from 0 to 6 nm. The impact of σ on higher-order harmonics (gm2 and gm3), voltage intercept point (VIP2 and VIP3), input intercept power (IIP3), intermodulation distortion (IMD3), and 1 dB compression point is investigated to study the reliability and linearity of GM TFET.

Cylindrical Nanowire-TFET with Core-Shell Channel Architecture: Design and Investigation

In this paper, a general gate-all-around (GAA) Tunnel Field Effect Transistor (TFET), TFET with novel extended source and drain structure as core-channel regions have been described. In this work, a comparison of the device performance of the cylindrical nanowire-GAA structure, core-extended source GAA structure and core-extended drain GAA structure is presented. Various device parameters like the non-local band to band tunneling, electron concentration, hole concentration, electric field, potential, the gate-to-gate capacitance and transfer characteristics are analyzed. Other important parameters are linearity parameters, which define the distortions and linearity of the device such as Third-order harmonics distortion (HD3), Third-order current intercept point (IIP3), Third-order intermodulation distortions (IMD3) and Third-order Voltage intercept point (VIP3). The increased gate control is observed in the core-extended source/drain structure. The core-extended based source-drain structure has improved the subthreshold by 5 mV/dec and ON-state current by 2 folds. The proposed design can help in improving the gate-all-around structure in terms of analog and linear characteristics.

Optimization of the geometry of a charge plasma double-gate junctionless transistor for improved RF stability

The radiofrequency (RF) stability of a charge plasma double-gate junctionless transistor (DG-CPJLT) is reported based on the stability factor (K) obtained from the Y-parameters of the device. The impact of variation of geometrical parameters, voltage biases, temperature, and interface traps on the stability of the DG-CPJLT is studied. Based on the results, an optimized DG-CPJLT device is designed and its RF figures of merit obtained. S-parameter values are also computed to study the high-frequency behavior of the device. Moreover, parameters for evaluation of the linearity, such as the third-order transconductance coefficient (gm3) and third-order voltage intercept point (VIP3), are also obtained for the optimized device. It is found that the DG-CPJLT shows significantly improved stability without affecting the RF figures of merit.

Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level

In this paper, a low band gap material and hetero-dielectric based silicon germanium source nano wire TFET (SiGe-S-NW-TFET) is created and compared with conventional silicon nano wire TFET (Si-NW-TFET). Both devices are analysed for its DC and RF/Analog performance. Proposed device achieves higher ON-current and steeper characteristic. Simulated results of RF analysis validate the device suitability for analog application as it attains high transconductance, cut-off frequency and GBP. Apart from this, linearity analysis is also done in terms of various FOMs like higher order of gm, second-order voltage intercept point, third-order voltage intercept point and third-order intermodulation distortion. Furthermore optimization of proposed device is also done for different diameter and channel length. For checking the device suitability in low power application two stage operational amplifier is implemented using unique characteristic of SiGe-S-NW-TFET which exhibits a high gain, high PSRR and GBW of 90.5 db, −47.4 dB and 78.61 MHz respectively. The objective of this paper is to attract the attention of semiconductor industry to find opportunity beyond CMOS technology. As NW-TFET structure has very low OFF-current it consumes very low power of 4.45 μW which ensures device applicability in low power application.

Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics

For the first time, we have explored the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field-effect transistor (HD-CP-TFET). The heterogeneous gate dielectric is considered to improve the ON-state current and device performance. The main intention of this work is to improve the drain current, transconductance characteristics along with linearity figure-of-merits (FOMs). A comparative analysis is done with conventional CP-TFET in the presence of interface trap charges (ITCs). From comparative results, it is found that the proposed device shows a better performance in the presence of interface trap charges. All the simulations are performed on ATLAS TCAD device simulator. The results show that the proposed device has a better tunneling current, transconductance (\(g_{\text {m}}\)), cut-off frequency (\(f_{\text {T}}\)), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3). Thus, the proposed device (HD-CP-TFET) shows the better performance in the presence of interface trap charges and indicates that this device is suitable for low-voltage analog/RF applications.