Abstract
In this paper, the proposed design of H-shaped TFET has been discussed. This design is providing a high Ion/Ioff ratio with a better Ion. HfO2 is used for better tunnelling current. The controllability of gate voltage on the drain current improves as the gate area increases. We can obtain better outcomes for current in this design by altering the architecture. With this device, Different parameters such as unit parameter, analog parameter, and linearity parameter have been studied and investigated the output of the H-TFET. As unit parameters, the electric field, electric potential, energy band diagram, and non-local band-to-band tunnelling rate (BTBT) have all been observed. Second and third-order harmonics distortion (HD2, HD3), third-order current intercept point (IIP3), third-order intermodulation distortions (IMD3), and second and third-order voltage intercept point (VIP2, VIP3) are evaluated as linearity parameters that characterize the device’s distortions and linearity. We obtained Ion\({\text{=1.6x}10}^{-4}\) A/μm,Ioff=2.1\({\text{x}10}^{-19}\) A/μm, Ion/Ioff=7.6\({\text{x}10}^{14}\),threshold voltage Vt=0.3449 V. © 2017 ElsevierInc.Allrightsreserved.
Highlights
We all required a device which has low power consumption, high speed and low area
The exact type of behaviour of H-TFET can be seen in device parameters like electron/hole concentration, electric field variation, potential variation energy band diagram, and nonlocal band to band tunnelling rate (BTBT)
It is obvious that no tunnelling is feasible in the OFF state, so its OFF current (Ioff) is very weak, while tunneling is possible in the ON state
Summary
We all required a device which has low power consumption, high speed and low area. This requirement is done by scaling of device. Because of the band-to-band tunneling (BTBT) process in TFETs, they have a lower ON-current (Ion) than traditional MOSFETs [1]. The current in a MOSFET [1] is measured by the thermionic emission of free charge carriers It is primarily from BTBT in TFET [5]. The proposed structure of Overlapped gate-source/drain H-shaped TFET is shown in fig. The proposed structure of Overlapped gate-source/drain H-shaped TFET is shown in fig1 In this design, we have gate is surrounded by channel for more tunneling. Overlapped area by gate on channel is responsible for the controllability of gate and it effects the tunneling rate of carriers. The non-local BTBT model depicts correct charge carrier tunnelling [14] in the system, with tunnelling occurring at the Source-Channel interface.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
