Transmission Gate Logic Research Articles

Statement of Removal: Design and analysis of 1-bit hybrid full adder cells for fast computation

ABSTRACT This research article introduces a 1-bit Full Adder (FA) cell comprising 20 transistors, employing Gate Diffusion Input (GDI) and transmission gate logic. The FA cell is segmented into four modules: the first module encompasses an AND-OR module, followed by a module housing a Multiplexer (MUX) based on transmission gates for Carry Output generation. The remaining two modules are XOR gates dedicated to Sum Output generation. Simulation of the proposed design is conducted on the 45 nm technology node using Cadence Virtuoso and its GPDK 45 nm library. To validate the performance of the proposed design, it is compared against existing full adders. Performance parameters such as power consumption, delay and Power Delay Product (PDP) demonstrate superior performance across voltages ranging from 0.8 V–1.2 V.

Design of Area Efficient, Low Power, High Speed 8-Bit Array Multipliers by Using Transmission Gate Logic

Design of Area Efficient, Low Power, High Speed 8-Bit Array Multipliers by Using Transmission Gate Logic

Optimization of 4-bit absolute value detector based on CMOS and PTL

This article designed and optimized a 4-bit absolute-value detector mostly using Complementary Metal Oxide Semiconductor (CMOS) static logic and transmission gate logic (PTL). In terms of overall architecture, the implementation of logic circuit functions is primarily separated into two modules, including the absolute value detector and the comparator. This paper identified the critical path of the final detector and conducted research and simplification on it to improve the general functionality of the detector which can compare the value of two numbers. To shorten the delay time in the circuit, this paper reduced the number of components on the crucial path. After calculating, the critical path delay is approximately 61.065 and the initial energy consumption for a minimum path delay is 51.06. To obtain the least amount of delay and energy use, three different techniques were used in this investigation. Ultimately, we found that the circuit optimized using the Changing V_DD and Sizing method was the most efficient. The optimized critical path delay remained around 61.065, and the energy consumption under optimized critical path delay was reduced to 10.845. The final implementation achieved a decrease of 82.2% in energy consumption while maintaining the critical path delay unchanged.

Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS

In this paper, we propose a novel design of a one-hot transmission-gate multiplexer (OTG-MUX), which combines Complementary Metal Oxide Semiconductor (CMOS) logic with Transmission Gate (TG) logic. We employ four techniques to enhance the performance: (1) propose a compact 8-transistor 2:1 TG-MUX2 cell to reduce the basic cell’s overhead; (2) apply the “wire-AND” technique to reduce the cells’ number by nearly half; (3) introduce a cascading scheme to float most of the circuit nodes, which significantly reduces the nodes that need to be charged; (4) optimize the placement and routing to enhance the layout’s utilization rate. Compared to the 1024:1 MUX based on the 12T CMOS standard MUX cell, our OTG-MUX achieves a 27.97% reduction in delay and a 98.16% decrease in power consumption. The simulation results indicate that the proposed OTG-MUX presents an appealing alternative for designing data scheduling modules in modern microprocessors.

Performance Analysis of 8-Bit Carry Select Adder

In this study, we evaluated the performance of an 8-bit carry-select adder (CSA) implemented through transmission gates for various metrics such as speed and area. Adders are an important part of digital computer systems and are used to perform additional operations. CSA is a well-known adder type known for its fast performance. Our results suggest that CSA implemented using transmission gates may improve the performance of digital circuits by achieving faster performance due to the low resistance and fast switching properties of these gates. In addition, we also analyzed the area utilization of CSA by measuring the number of transistors in the synthesized design. The integration of transmission gates into the CSA can affect area characteristics and our analysis provides insight into the design's area efficiency. CSA was developed in this study using transmission gate technology along with MTCMOS D-latch to achieve superior performance compared to previous studies. Simulations were performed using 250nm CMOS technology from Tanner and Mentor Graphics. His CSA implementation with transmission gate logic significantly reduced transistor count by 58.85% compared to his conventional CSA. This approach was chosen for its better results and improved overall performance.

Design of Wallace Tree Encoder for Flash ADC

Analog to digital converter plays a very important role in today’s digitized world as they have wide range of applications. Wallace tree encoder is an effective hardware implementation in VLSI circuits that is utilized for the analogue to digital conversion process. The Wallace tree encoder transforms thermometer code into binary code in an ADC. The suggested flash digital to analogue converter confirmed the energy, and speed. The proposed technique provides Less Delay, Less Power Consumption, and a lesser number of transistors compared to existing techniques. In this project, the proposed transmission gate full adder technique provide Less Delay, Less Power Consumption, Better Power Delay Product and a lesser number of transistors. The proposed encoder is made to count the 1s available to the logic gates for designing ROM encoders and fat tree conversion. The power may be conserved by building a low power, high performance Wallace tree encoder implementing transmission gate logic and modified full adders since Wallace tree encoder uses more power. The proposed system focuses at lowering the transistor count to improve power efficiency and delay comparator, and it is effective in minimizing the bubble errors. The Wallace tree encoder is designed by using transmission gate based full adder circuits. The proposed designs are designed and simulated using LTspice Tool with 45nm CMOS technology. The power consumption of the encoder circuit must be decreased in order to create a low power Flash ADC. The power consumption of this encoder changes noticeably when the internal full adder circuit is modified

A Low Energy Depletion CMOS Transistor-based 4-bit Absolute-value Detector

With the development of the electronic industry, the requirements for equipment are becoming higher and higher in recent years. In this paper, a 4-bit absolute value detector is designed to have a low delay and energy consumption. The detector is composed of MUX, an adder, and a comparator. By comparing the 4-bit input with the given threshold value, the result is output. Based on the logic effort theory, this paper calculates the logic effort and parasitic delay of each stage of the detector and uses the transmission gate logic to redesign the XOR gate, which greatly improves its performance. Through certain calculations and optimization, the delay and energy consumption of the detector is reduced. Finally, this paper realizes a relatively simple 4-bit absolute value detection circuit, which has a small number of transistors and greatly improves the performance of the circuit. At the same time, it has a certain reference value for the related circuit design.

Layout Design of Row Decoder using Cadence

Abstract: Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances

Image processing with high-speed and low-energy approximate arithmetic circuit

Nowadays there are plenty of compute-intensive algorithms that are carried out at the edge. Therefore, it is necessary to design low-energy and high-speed circuits. Approximate computing (AC) is an emerging paradigm that can be used in error-resilient applications such as multimedia processing. In this paper, a novel approximate full adder design is proposed with the aim of latency and energy consumption reduction at the cost of producing some errors at the output. The proposed design uses pass transistor and transmission gate logic styles to achieve these aims. The proposed cell and referenced circuits are applied in a vast range of simulation conditions including power supply, ambient temperature, and load variations. Moreover, the constancy of the proposed cell concerning the process variations of carbon nanotubes (CNTs) is studied. All circuits are implemented at the transistor level using carbon nanotube field-effect transistor (CNFET) technology. Experimental results based on HSPICE simulation indicate the superiority of the proposed cell in terms of latency, power-delay product (PDP), and energy-delay product (EDP) criteria against state-of-the-art designs. Moreover, at the application level, image blending is used to study the accuracy metrics such as peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) quantitative metrics. Finally, the PDP, PSNR, and SSIM metrics are simultaneously taken into account as a figure of merit (FOM) to trade-off between circuit and application-level metrics. Quantitative results confirm the better functionality of the proposed approximate full adder cell compared to its counterparts.

Design of FinFET based low power, high speed hybrid decoder for SRAM

This paper proposes a novel FinFET based hybrid logic design for line decoders, which comprises of transmission gate logic (TGL), modified gate diffusion input (MGDI) logic and conventional NAND based FinFET logic. The 2–4 FinFET based decoder is designed using two topologies: (i) a 14- transistor topology for low power dissipation and lesser area and (ii) a 15-transitor topology for high-speed performance. Using the two topologies mentioned above, both inverting and non-inverting decoders of size 2–4 and 4–16 are designed. SPICE simulations of the proposed decoders are done at 45 nm CMOS and FinFET technologies and compared with different logic styles such as conventional logic, MGDI, mixed logic, and mixed MGDI logic at different frequencies with varying supply voltages and the proposed design outperforms other logic styles compared. The proposed FinFET hybrid decoder exhibits 6% and 77% lower power; 11.6% and 61.26% lower delay; 17% and 91.10% lower PDP respectively compared to the FinFET mixed decoder and CMOS hybrid decoder.

PARAMETER ANALYSIS OF SRAM CIRCUIT

The study examined the different a number of power-saving strategies, including sleep, stack, sleep stack, transmission gate logic, or self-controllable voltage level- upper (SVL-U). These methods are used with SRAM cells that have 6 transistors (6T), 7 transistors (8T), 8 transistors (9T), and 10 transistors (10T). The SVL-U method and transmission gate logic are used in suggested SRAM cell. According to a comparison of SRAM memory array as well as cells, dynamic power is significantly decreased on average when compared to traditional methods. The 45nm and 90nm software applications from Cadence are also used for simulation. According to a thorough analysis of SRAM memory arrays and cells, PDP and EDP have, on average, been significantly decreased when contrasted the state-of-the- art hybrid VLSI techniques. Therefore, these SRAMs are suitable for extremely low power embedded structural appliances. Keywords: Semiconductor Memories, Memory organization, SRAM, Write operation, Read Operation.

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

AbstractThe very large‐scale integration (VLSI) design‐based architectures of 2‐D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2‐D digital filters. In this work, circular symmetry is adopted to optimize the 2‐D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal‐oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2‐D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2‐D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45‐nm CMOS technology. The final physical design layout‐area, power, and delay reports are correlated with existing state‐of‐artworks. It is found that the proposed 2‐D FIR filter outperforms the existing works.

Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications

Most of the full adder (FA) circuits are implemented through a hybrid logic style using three different modules. The principal peculiarity of these hybrid logic style-based FA cells is that each module could be optimized individually to improve the circuit performance. A high-performance 1-bit hybrid FA cell is proposed with pass transistor logic and transmission gate logic in the present work. The proposed FA circuit is implemented using 20-transistors to achieve optimum performance. The proposed circuit is simulated in Cadence virtuoso tool by using 90-nm process CMOS technology. Comparison of the design matrices for the proposed 1-bit hybrid FA cell against the five different reported FA circuits is also carried out. The present study reported 13.01–54.93 % and 13.01–59.20 % improvement in terms of delay and power delay product (PDP), respectively, compared to other FA designs. The proposed circuit is also investigated in different supply voltages (0.6–1.5V). Furthermore, the FA circuit is verified in different process corner conditions to check the robustness.

Ternary Logic Circuit Based on Negative Capacitance Field-Effect Transistors and Its Variation Immunity

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at ${V}_{\text {DD}}$ /2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NM $_{M}$ ) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization ( ${P}_{r}$ ) and coercive electric ( ${E}_{C}$ ) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states.

Power Efficient Clock Pulsed D Flip Flop Using Transmission Gate

The need for low-power sequential circuits is pushing towards the implementation of low power consuming basic memory elements like D Flip-Flop. To accomplish power efficient D Flip-Flop, 180 nm CMOS technology is utilized to develop a novel eminent performance Current-Mode Pulse Triggered D Flip-Flop. Instead of voltage utilization in clock distribution is the new idea in the developed method uses current to render low power consumption clock signal. D Flip-Flop is designed by transmission gate which is also reduces the power consumption along with Current-Mode signaling. The Cadence - Virtuoso tool is to be used to simulate all the circuits with 180nm technology. Power consumption reduction in the designed D Flip-Flop is the foremost and major aim of the project. For reducing, power consumption in D Flip-Flop we are employing two methods. They are, Use of Current Mode Clock Distribution Networks (CM-CDN) instead of Voltage Mode Clock Distribution Networks (VM-CDN). Use of Transmission Gate Logic to implement the D Flip-Flop, instead of Static CMOS Logic.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

WITHDRAWN: Implementation of low power one bit full adder with cadence tool

Abstract In this research paper, the one-bit low power hybrid adder circuit is developed by additional logic of direct polarization and the reverse polarization method (FSB / RSB) of the Complementary metal-oxidesemiconductor (CMOS) and Transmission Gate Logic (TGL). A full adder of 1-bit is proposed in 180 nm technology and the performance parameters, such as delays, strengths, and areas, are compared to such as CMOS, 10 T, 14 T, and Hybrid Connectors. The design uses a power supply of 1.8 V for 180 nm technology. Compared to other existing full additive designs, there is a better improvement in the strength of the proposed adder and PDP reference.

A novel ultra-low power 7T full adder design using mixed logic

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”.Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T.Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T.But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

WITHDRAWN: Low power MUX using mixed logic

Abstract A mixed logic design method for Multiplexer is introduced in this paper, transmission gate logic (TGL), pass transistor dual value logic (DVL) and static CMOS are used in this proposed design. A line decoder is used in this design. The line decoder consists of TGL and DVL gates. Compared to traditional multiplexer design topology has less transistor count. Since there are less transistors design is aimed for low power dissipation. Finally, a variety of simulations in microwind at the 7 nm shows a significant improvement in power, outperforming CMOS in almost all cases.