Design of FinFET based low power, high speed hybrid decoder for SRAM

Abstract

This paper proposes a novel FinFET based hybrid logic design for line decoders, which comprises of transmission gate logic (TGL), modified gate diffusion input (MGDI) logic and conventional NAND based FinFET logic. The 2–4 FinFET based decoder is designed using two topologies: (i) a 14- transistor topology for low power dissipation and lesser area and (ii) a 15-transitor topology for high-speed performance. Using the two topologies mentioned above, both inverting and non-inverting decoders of size 2–4 and 4–16 are designed. SPICE simulations of the proposed decoders are done at 45 nm CMOS and FinFET technologies and compared with different logic styles such as conventional logic, MGDI, mixed logic, and mixed MGDI logic at different frequencies with varying supply voltages and the proposed design outperforms other logic styles compared. The proposed FinFET hybrid decoder exhibits 6% and 77% lower power; 11.6% and 61.26% lower delay; 17% and 91.10% lower PDP respectively compared to the FinFET mixed decoder and CMOS hybrid decoder.