Low-Power and High-Speed 2-4 and 4-16 Decoders Using Modified Gate Diffusion Input (M-GDI) Technique

Abstract

This paper introduces the design of 2-4 and 4-16 line decoders using modified version of gate diffusion input (M-GDI) technique as it reduces the area that is the number of transistors and also it reduces the dissipation of power. The Combinational circuits like decoders which are used in the periphery circuitry of memory arrays like Static RAM are designed by using Modified Gate Diffusion Input (M-GDI) technique which eradicate the disadvantages of the pass transistor logic (PTL) and CMOS logic. The decoders which are designed using modified GDI technique offer better characteristics in terms of average power and delay, and also the transistor count is reduced compared to the decoders which are designed using mixed logic technology which are static CMOS, pass transistor logic and transmission gate logic. Finally, the decoders which are designed by using two techniques in 90 nm technology using Cadence Virtuoso compared in terms of transistor count, average power, delay and power delay product (PDP) show an improvement when compared to the decoders of mixed logic.