Performance Analysis of 8-Bit Carry Select Adder

Abstract

In this study, we evaluated the performance of an 8-bit carry-select adder (CSA) implemented through transmission gates for various metrics such as speed and area. Adders are an important part of digital computer systems and are used to perform additional operations. CSA is a well-known adder type known for its fast performance. Our results suggest that CSA implemented using transmission gates may improve the performance of digital circuits by achieving faster performance due to the low resistance and fast switching properties of these gates. In addition, we also analyzed the area utilization of CSA by measuring the number of transistors in the synthesized design. The integration of transmission gates into the CSA can affect area characteristics and our analysis provides insight into the design's area efficiency. CSA was developed in this study using transmission gate technology along with MTCMOS D-latch to achieve superior performance compared to previous studies. Simulations were performed using 250nm CMOS technology from Tanner and Mentor Graphics. His CSA implementation with transmission gate logic significantly reduced transistor count by 58.85% compared to his conventional CSA. This approach was chosen for its better results and improved overall performance.