Area and power efficient carry select adder using 8T full adder

Abstract

Carry select adder (CSLA) one of the fastest adders used in complex data processing to perform fast arithmetic functions. Minimum amount of power consumption is a major driving force behind the development of CMOS technologies. From the structure of CSLA it is clear that there is scope for reducing the area & power consumption in the CSLA. In this paper 8T full adder is used as a building block for 8-bit SQRT CSLA. 8T full adder is designed by XNOR-XNOR hybrid CMOS design. Based on this modification, 8-, 16-, 32-, 64-bit SQRT CSLA architecture has been developed & compared with the regular SQRT CSLA. Binary to Excess one converter (BEC) based CSLA are analyzed to study the data dependence & to identify all redundant logic operations. In this paper, all the redundant logic operations in the conventional CSLA are eliminated and a new logic formulation where carry select operation is scheduled before the calculation of final sum is proposed. Gate Diffusion Input (GDI) technique of low power digital combinatorial circuit design is also described. The frequency of operation is 5 MHZ. This work estimates the performance of the proposed design with the regular design in terms of area & power through the logic design & layout in 250nm CMOS process technology & implemented using Tanner (S-Edit) tool. The result analysis shows that the proposed structure is better than the conventional CSLA.