Transmission Gate Logic Research Articles

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme condi- tionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

Comparative Performance Analysis of Low Power Full Adder Design in Different Logics in 22nm Scaling Technology

This paper gives the comparison of performance of full adder design in terms of area, power and delay in different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles. This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.

CMOS Design Of Low Power High Speed Hybrid Full Adder

In this paper, the design of hybrid full adder CMOS design is presented. There are various design modules are used to implement the hybrid full adder design. Transmission gate logic based hybrid full adder design is implemented in this paper by using complementary metal oxide semiconductor (CMOS) logic for low power applications. In general, the full adder performance evaluation is analyzed for 1 bit and these design bit size is extended up to 4 bit for various applications like ALU Unit. For high speed applications, the proposed design is used and also it reduces the delay and power than existing design. Extended 4-bit full adder is performed with low power voltages and reduced number of transistor counts. There are various logic is used to design a full adder to check the synthesis comparisons through schematic design.Proposed design is designed in S-Edit, these output waveform and simulation results are evaluated in T-Spice by using Tanner EDA Tool.

Design of Low Power CMOS Parallel Prefix Adder Cell

Addition is the basic operation in many modern electronic applications. As the fastest adder, parallel prefix adder is of most interest for many circuit designers. For the past few decades, supply voltage and the size of transistors have been reduced tremendously. With more and more transistors being integrated on one single chip, the power issue must be taken care of. Low power adder has been studied for years and many solutions are proposed. In this paper, a new circuit is designed at transistor level. The proposed circuit cell employs transmission gate logic and a MUX-based structure. Simulations are conducted using Cadence® Virtuoso Spectre Simulator. The result shows that the new adder demonstrates a better performance in terms of power dissipation, which saves more than 5% energy compared with Conventional CMOS logic adders with different word length.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic

The main issue in designing of VLSI circuits is power consumption and area requirement In this paper Multiplexer circuit is proposed with the help of transmission gate logic using 6 transistors. Different design methodologies are used for designing of multiplexer layout. Multiplexer is essential circuit for different field of network and communication. Multiplexer requires less number of transistors using transmission gate logic. The main concerned of this paper is to reduce area, power consumption and complexity of Multiplexer using different design methodologies.

Ultra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold Regime

The computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission gate logic have been proposed to optimize the overall Power-Delay-Product (PDP). The proposed compressors are also used in the design and comparative analysis of 4×4-bit and 8×8-bit Wallace and Dadda multipliers operating in sub-threshold regime. The multipliers based on the proposed compressor designs have been simulated using 45 nm CMOS technology at various supply voltages, ranging from 0.3 to 0.5 V. The result shows on an average 89% improvement in the PDP of the proposed compressor blocks, when compared with the existing published results in sub-threshold regime. The multipliers designed using the proposed compressor blocks also show improved results.

Transmission Gate base Programmable Binary Incrementer Decrementer

We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle. For this, design of a faster and highly reliable adder is of major importance. Thus, much effort has been invested in the research that has led to faster and more efficient ways to perform this operation. To prove the efficiency of the proposed method, the circuit is simulated in pass transistor CMOS 50nm technology and some simulation parameters are calcultes in the layout of the circuit. The binary decrementer reduces the stored binary data in memopry or register by ‘1’. This can be done by using 2’s complement method by using XOR gates which convert binary data in 1’s complement and then by addition of binary ‘1’ it can be converted to 2’s complement form. It is made by cascading ‘n’ full adders for ‘n’ number of bits i.e. the storage capacity of the register to be decremented. Hence, a 4-bit binary decrementer requires 4 cascaded half adder circuits. This paper presents the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs. Our design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area.

Ultra Low Power Consumption Military Communication Systems

New military communications require increased versatility for the transmission of a wide range of data, voice and images. There are many algorithms needed for communication like FFT (Fast Fourier Transform), DCT (Discrete Cosine Transforms), Viterbi coders and decoders, trellis techniques etc. Advances in VLSI technology continue to improve the quality of algorithm that can be implemented on a single die. But even though all these algorithms implementable on a single chip, they require large amount of computation and consequently require large die area and high levels of power dissipation. In wireless communication, Viterbi decoder which consumes more power plays an important role in communication applications. Viterbi decoder is used to decode the received data which is encoded using convolution codes, which has less probability of error compared to other coding techniques. In many digital systems like Viterbi decoder, multiplexers and XOR gates are the major building blocks, which are often designed using transmission gate logic. So, to reduce the power consumption and number of transistors count in the decoder design, the transmission gates are replaced with the pass transistors which contain only one NMOS transistor. Since the eliminated PMOS transistor is large in size, the capacitance in the circuit is reduced thereby reducing the power, size and increase in the speed. This technique is simulated using TANNER tool. The improved performance of Viterbi decoder using pass transistor logic is compared with that of the transmission gate logic and results were compared using TANNER tools. General Terms Viterbi decoder algorithm, The branch metric (BM) , The path metric, Tanner Tools.

A High Speed Low Power Adder in Multi Output Domino Logic

Speed and power is the major constraint in modern digital design. We have to design the high speed, l ess number of transistor as a prime consideration. The low power c arry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass t ransistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit ad ders and then shortening the path to reduce the total critical pa th delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power consumption in microwatt range.

Power Optimization of 8:1 MUX using Transmission Gate Logic (TGL) with Power Gating Technique

This paper aims at reducing power and energy dissipation in Transmission Gate Logic (TGL) Multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current and delay with economical charge recovery logic. This paper designs an 8:1 Multiplexer with CMOS Transmission Gate Logic (TGL) using the Power Gating Technique, which reduces the leakage power and leakage current in active mode. Power Gating Technique uses Transmission Gate Logic (TGL) based an 8:1 multiplexer circuit which removes the degraded output. The PMOS and NMOS transistors are connected together for strong output level. Power gating technique achieves 36% reduction of leakage current and 43% reduction of leakage power in active mode, A the results of this paper are simulated on cadence virtuoso tool realized in 45nm technology with reduction of 4.021fW power, 7.381pA current and 0.7V supply voltage.

High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic

In this paper, we propose counter type ADC for high-speed applications. Counter type ADCs are one of the most popular ADC topology used to implement moderate resolution converter due to their reasonably fast conversion time and simplicity.. Designed ADC has 8 input channels each of which has 0 – 2.6 V signal range. The resolution of ADC the converter is 8 bits. The amount of passing through a system from input to output ADCs can be increased by using its technique This is implemention on the circuit level with pass transistor circuit. The primary focus of this work design and implementation of a pass transistor based Analog-to-Digital converter. The proposed counter type ADC is composed of a 8-bit DAC design by using transmission gate logic, a comparator logic , 8 bit digital counter and “AND” gates to pass the clock signal by considering the chip area, operation speed, and circuit complexity.

High performance, low power 200 Gb/s 4:1 MUX with TGL in 45 nm technology

The various analysis are established more on arithmetic circuits particularly with MUX design, this paper also explores with multiplexer to optimize the power. The CMOS transmission gate logic (TGL) is used to design a new 4:1 MUX with reduction in circuit complexity compared to conventional CMOS based multiplexer design. Based on TGL, it removes the degraded output, the NMOS and PMOS are combined together for strong output level with the gain in area, which is a central result of proposed MUX. The designed circuit is realized in 45 nm technology, with the power dissipation of 1.887 nW from a 0.7 V supply voltage. The MUX can operate well up to 200 Gb/s.

Full-Custom Design and Implementation of High-Performance Multiplier

I proposed a method of using full-custom design 32 × 32 multiplier to enhance performance, reduce the power consumption and the area of layout. I use improved Wallace tree structure for partial product compression, truncated beyond the 64 part of the plot and the look-ahead logarithmic adder using Radix-4 Kogge-Stone tree algorithm raise the multiplier performance. In the design of Booth2 encoding circuit and compression circuit, I use a transmission gate logic design with higher speed and smaller area. I also use Euler path method and heuristic Euler path method to reduce the layout area. The design use SMIC 0.18μm 1P4M CMOS process, with a layout area of 0.1684mm2. In a large number of test patterns, simulation results show that the computation time of a 32 × 32 multiplication is less than 3.107ns.

Design of High-Speed Adders for Efficient Digital Design Blocks

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

A VLSI array architecture for realization of DFT, DHT, DCT and DST

A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (coordinate rotation digital computer) arithmetic unit as the basic processing element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throughput. Moreover, the simple local neighborhood interprocessor connections make it convenient for VLSI implementation. The architecture can be extended to compute transformation of longer length by judicially cascading the modules of shorter transformation length which will be suitable for wafer scale integration (WSI). CORDIC is designed using transmission gate logic (TGL) on sea of gates semicustom environment. Simulation results show that this architecture may be a suitable candidate for low power/low voltage applications.

5 Gbit/s 2:1 multiplexer fabricated in 0.35 µmCMOS and3 Gbit/s 1:2 demultiplexer fabricated in 0.5 µm CMOStechnology

The authors have designed two dynamic CMOS circuits (based on dynamic transmission gate logic), a 5 Gbit/s 2:1 multiplexer and a 3 Gbit/s 1:2 demultiplexer, which can be used in the place of their counterpart CML circuits. Both circuits feature front-end amplification to convert CML levels to CMOS logic swings, and open drain output drivers with CML levels into 50 Ω.

My-box representation for faulty CMOS circuits

A new logic element, My-box, is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits, which consist of fully CMOS logic, pseudo NMOS logic, dynamic CMOS logic, clocked CMOS (C/sup 2/MOS) logic, CMOS domino logic and NORA CMOS logic. It can also be used to model the faults and the functions of a transmission gate logic. A procedure is described to transform a transistor level CMOS circuit to a gate-level equivalent circuit which is composed of AND, OR and the My-box logic element. A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit. By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS logic.