A High Speed Low Power Adder in Multi Output Domino Logic

Abstract

Speed and power is the major constraint in modern digital design. We have to design the high speed, l ess number of transistor as a prime consideration. The low power c arry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass t ransistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit ad ders and then shortening the path to reduce the total critical pa th delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power consumption in microwatt range.