Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS

Abstract

In this paper, we propose a novel design of a one-hot transmission-gate multiplexer (OTG-MUX), which combines Complementary Metal Oxide Semiconductor (CMOS) logic with Transmission Gate (TG) logic. We employ four techniques to enhance the performance: (1) propose a compact 8-transistor 2:1 TG-MUX2 cell to reduce the basic cell’s overhead; (2) apply the “wire-AND” technique to reduce the cells’ number by nearly half; (3) introduce a cascading scheme to float most of the circuit nodes, which significantly reduces the nodes that need to be charged; (4) optimize the placement and routing to enhance the layout’s utilization rate. Compared to the 1024:1 MUX based on the 12T CMOS standard MUX cell, our OTG-MUX achieves a 27.97% reduction in delay and a 98.16% decrease in power consumption. The simulation results indicate that the proposed OTG-MUX presents an appealing alternative for designing data scheduling modules in modern microprocessors.