Design and Analysis of Penta-Magnetic Tunnel Junction Circuit with Transmission Gate Logic

Abstract

AbstractThe design of very large-scale integrated circuits passes through many critical stages and challenges the advanced technology of nanometer CMOS technology. The major problem included in the existing process is the leakage current and reliability issues. Penta-magnetic tunnel junction (Penta-MTJ) hybrid with CMOS technology has many advantages in the VLSI strategy such as higher performance and low leakage current. The methodology of the proposed work includes the increase in the storage capacity with optimized power and speed using transmission gate logic and decrease in area and power in combinational and sequential circuits. The structure of Penta-MTJ includes the design of transmission gates to increase the speed with the minimum number of gates to reduce the area and power consumption. By decreasing the number of transistors in transmission gate logic, the power consumption was reduced to 12 and 18%. To overcome the sensing reliability issue, high sensing margin is proposed in the design circuit. With a 43.9 and 10.7% increase in energy delay product (EDP), the proposed approach reduces energy demand while incurring low area overhead.KeywordsPenta-magnetic tunnel junction (MTJ)Transmission gate logic (TGL)SpintronicsEnergy delay product