Transconductance Gm Research Articles

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

This paper presents a three dimensional (3-D) statistical simulation study of a 7 nm technology node SOI p-channel step-FinFET and compares with that of a conventional FinFET (c-FinFET). For the first time we have investigated the impact of various dimensional parameters like Gate Length (LG), Fin width (Wfin1 and Wfin2, Wfin = fixed), Fin height (Hfin1 and Hfin2, Hfin = fixed) and Fin-width ratio on the performance of c-FinFET and step-FinFET devices. These FinFET structures have been designed and simulated in Cogenda Visual TCAD under certain boundary conditions and the performance has been analyzed. The electrical parameters such as ON-current (ION), OFF-current (IOFF), Sub-threshold Swing (SS), Drain Induced Barrier Lowering (DIBL), threshold voltage (Vt) roll-off, Transconductance (gm) and Transconductance Generation Factor (TGF) are extracted. It is observed that short channel effects (SCEs) can be controlled by reducing Wfin1, decreasing major fin height (Hfin1) and increasing Gate length (LG) (14 nm to 20 nm). It is noticed that there is a significant improvement in ION/IOFF ratio from 1.01 × 104 to 1.41 × 105 with respect to increased channel length, SS of 76.68 mV/decade to 67.8 mV/decade and excellent DIBL of 55 mV/V in c-FinFET. For the proposed step-FinFET at LG = 16 nm there is improved DIBL of 85 mV/V compared to the c-FinFET, which can be further improved up to 64.63 mV/V by decreasing the Hfin1/Hfin2 ratio (4 to 0.25). The parametric analysis concludes that step-FinFET is more susceptible to SCEs in terms of DIBL, Vt roll-off as compared to the c-FinFET. This work considers LG = 16 nm for analysing the dimensional variation effect on both the devices. In contrast c-FinFET is more preferable than the proposed device at lower technology nodes.

Threshold voltage instability and hysteresis in gamma-rays irradiated 4H-SiC junction field effect transistors

High dose irradiation effects of gamma-rays up to 17 MGy (H2O) on 4H-SiC junction field effect transistors (JFETs) were investigated. Due to the irradiation, gradual positive threshold voltage (Vth) shift as high as 0.5 V and continuous decrease in transconductance gm were observed. In addition, Vth instability and hysteresis appeared for the irradiated JFETs when the gate voltage (VG) sweep direction, sweep interval, i.e., averaged sweeping rate, sweep range, and delay time were changed. Increase of VG interval attributed to positive Vth shift for both forward and reverse directions, whereas narrowing of sweep range and increase of delay time resulting in a more noticeable negative shift of Vth for the reverse direction. Such Vth hysteresis indicates that capture and release of carriers predominantly took place via hole traps formed around the gate region due to high dose gamma-ray irradiation.

Performance Assessment and Optimization of Vertical Nanowire TFET for Biosensor Application

This paper reports the performance assessment of vertical silicon nanowire TFET (V-siNWTFET) design for biosensor applications using dielectric-modulation and gate underlap technique. The sensitivity of the V-siNWTFET is recognizing by immobilizing the different biological molecules such as lipids, biotin, uricase, protein, Gox, streptavidin, uriease, zein etc. in the cavity region which is created under the gate electrode and source oxide. The performance analysis is observed by varying the relative permittivity of the different biomolecules and analyzes the parametric variation both for neutral and charged biomolecules. The sensitivity of the biosensor has been detecting in the terms of drain current (ID), threshold voltage (VTH), subthreshold slope (SS), transconductance (gm), and ION/IOFF ratio. The proposed device structure has capable to reduce the leakage currents and high sensitivity biosensor design in the nanoscale regimes. The obtained best optimum parameters of the proposed devices are ION (1.37E−08 A/µm), IOFF (9.44E−19 A/µm), SS (29.97 mV/dec) and ION/IOFF (4.29E + 10) ratio with gate work-function (ϕgate = 4.8 eV) and uniformly doped (1 × 10–19 cm−3) silicon nanowire at drain to source voltage (VDS = 1.0 V). The higher sensitivity of the proposed V-siNWTFET for Biosensor is observed for Zein biomolecules (K = 5).

A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement

In this paper, we report, the hot carrier reliability issue in the Si1-xGex source/drain nanotube (NT) junctionless field-effect transistor (JLFET) with temperature variations. The surface potential, electric field and drain current have been formulated by developing a physics-based analytical model. SiGe in the source/drain regions creates valence band discontinuity of ΔEg = 0.23 eV which significantly increases the tunneling width at the channel/drain interface and therefore, results in a diminished L-BTBT action. The results demonstrate that at T = 500 K, drain current with the influence of interface trap charges in the Si1-xGex S/D architecture shows better immunity than the conventional NTJLFET. The Si1-xGex S/D enhances the reliability of analog/RF parameters such as transconductance (gm), intrinsic gain (gm/gd), cut-off frequency (fT), and gain-transconductance-frequency-product (GTFP), against the hot carriers. We have also explored the reliability with germanium (Ge) content, x and observed that for Ge content above x = 0.3, the reliability degrades in terms of higher electron temperature, reduced gm, and lower fT. The analytical results are verified and are in good agreement with results of Sentaurus TCAD simulations. The Si1–xGex S/D architecture combined with NT core gate can help relieve the HCI trap charge reliability for JLFETs leading to significantly improved analog/RF parameters.

Fast-Scanning Potential-Gated Organic Electrochemical Transistors for Highly Sensitive Sensing of Dopamine in Living Rat Brain.

Developing techniques for the highly sensitive assay of neurotransmitters is essential for understanding physiological and pathological processes. Here, we demonstrate a fast-scanning potential (FSP)-gated organic electrochemical transistor (OECT): for the highly sensitive sensing of dopamine (DA) in a living rat brain. The configuration combines the selectivity of fast-scan cyclic voltammetry (FSCV) with the high sensitivity of an OECT. The combined use of FSP as a gating mode and transconductance (gm ) as a sensing parameter further improve the sensing performance in terms of sensitivity, limit of detection, reproducibility, and stability. The FSP-OECT exhibits a sensitivity of 0.899 S M-1 and a low limit of detection down to 5 nM and was validated for in vivo monitoring of the basal level and electrically stimulated release of DA.

Fast‐Scanning Potential‐Gated Organic Electrochemical Transistors for Highly Sensitive Sensing of Dopamine in Living Rat Brain

AbstractDeveloping techniques for the highly sensitive assay of neurotransmitters is essential for understanding physiological and pathological processes. Here, we demonstrate a fast‐scanning potential (FSP)‐gated organic electrochemical transistor (OECT): for the highly sensitive sensing of dopamine (DA) in a living rat brain. The configuration combines the selectivity of fast‐scan cyclic voltammetry (FSCV) with the high sensitivity of an OECT. The combined use of FSP as a gating mode and transconductance (gm) as a sensing parameter further improve the sensing performance in terms of sensitivity, limit of detection, reproducibility, and stability. The FSP‐OECT exhibits a sensitivity of 0.899 S M−1 and a low limit of detection down to 5 nM and was validated for in vivo monitoring of the basal level and electrically stimulated release of DA.

A Method to Measure Polarization Signal of Nanoscale One-Transistor-One-Capacitor Ferroelectric Memory

This study investigates the properties of a onetransistor- one-capacitor (1T1C) device that includes a transistor and ferroelectric random access memory (FeRAM) at the nanoscale. The hysteresis characteristics are presented. A simultaneous measurement of writing and reading was used. A difference was observed between the forward and reverse transconductance (gm) −V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> curves, and the reason can be explained by the relationship between the operating voltage and coercive voltages. According to the relationship between gm and polarization, the polarization signal can be obtained using gm at the nano-scale. The remnant polarization of the 1T1C device per unit ferroelectric-layer area was confirmed by the polarization value of FeRAM via the Positive Up Negative Down method. Finally, the P–V loops obtained using gm values with different measurement ranges are also reported.

Simulation of Junctionless Transistor for Low Power Mix Circuit

Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction transistor.

Direct Electrochemical Signaling in Organic Electrochemical Transistors Comprising High-Conductivity Double-Network Hydrogels.

In composite hydrogels, the high electrical performance of poly(3,4-ethylenedioxythiophene) complexed with poly(styrenesulfonate) (PEDOT:PSS) is integrated with complementary structural and electrochemical functions via a rationally designed poly(acrylamide) second network incorporating phenylboronic acid (PBA). Free-standing double-network hydrogels prepared by a simple one-pot radical polymerization exhibit state-of-the-art electrical conductivity (∼20 S cm-1 in phosphate buffered saline) while retaining a degree of hydration similar to that of biological soft tissues. Low resistance contacts to Au electrodes are formed via facile thermo-mechanical annealing and demonstrate stability over a month of continuous immersion, thus enabling hydrogels to serve as channels of organic electrochemical transistors (OECTs). Despite thicknesses of ∼100 μm, gating of hydrogel OECTs is efficient with transconductances gm ∼ 40 mS and on/off ratios of 103 in saturation mode operation, whereas sufficiently high conductivity enables linear mode operation (gm ∼ 1 mS at -10 mV drain bias). This drives a shift of sensing strategy toward detection of electrochemical signals originating within the bulky channel. A kinetic basis for glucose detection via diol esterification on PBA is identified as the coupling of PBA equilibrium to electrocatalyzed O2 reduction occurring on PEDOT in cathodic potentials. Hydrogel OECTs inherently amplify this direct electrochemical signal, demonstrating the viability of a new class of soft, structural biosensors.

Cyano-Functionalized n-Type Polymer with High Electron Mobility for High-Performance Organic Electrochemical Transistors.

n-Type organic mixed ionic-electronic conductors (OMIECs) with high electron mobility are scarce and highly challenging to develop. As a result, the figure-of-merit (µC*) of n-type organic electrochemical transistors (OECTs) lags far behind the p-type analogs, restraining the development of OECT-based low-power complementary circuits and biosensors. Here, two n-type donor-acceptor (D-A) polymers based on fused bithiophene imide dimer f-BTI2 as the acceptor unit and thienylene-vinylene-thienylene (TVT) as the donor co-unit are reported. The cyanation of TVT enables polymer f-BTI2g-TVTCN with simultaneously enhanced ion-uptake ability, film structural order, and charge-transport property. As a result, it is able to obtain a high volumetric capacitance (C*) of 170±22F cm-3 and a record OECT electron mobility (μe,OECT ) of 0.24 cm2 V-1 s-1 for f-BTI2g-TVTCN, subsequently achieving a state-of-the-art µC* of 41.3 F cm-1 V-1 s-1 and geometry-normalized transconductance (gm,norm ) of 12.8 S cm-1 in n-type accumulation-mode OECTs. In contrast, only a moderate µC* of 1.50 F cm-1 V-1 s-1 is measured for the non-cyanated polymer f-BTI2g-TVT. These remarkable results demonstrate the great power of cyano functionalization of polymer semiconductors in developing n-type OMIECs with substantial electron mobility in aqueous environment for high-performance n-type OECTs.

Low Leakage and High ION/IOFF Ratio in Partial Gated AlGaN/GaN Nanowire Field‐Effect Transistors

Lateral nanowire (NW) field‐effect transistors are fabricated by a top‐down approach on an AlGaN/GaN heterostructure. A combination of dry and anisotropic wet etching is used to form the NW. The channel is controlled by a 2D electric field originating from two partial gates on the parallel sides of the nanowire channel. While a larger overlap of the gate with the channel region, as in a gate‐all‐around transistor, improves gate control in terms of transconductance gm, gate leakage current and ION/IOFF deteriorate. Partial overlapping gate transistors are found to provide a trade‐off, providing extremely low gate leakage current (≈10 μA cm−2), very low IOFF (100 fA μm−1), and very high ION/IOFF (5 × 108). Despite the nature of the partial gate, a good subthreshold swing (SS) of ≈79 mV decade−1 is observed. Various transistor performance parameters can be tuned within a certain window of trade‐offs between them as the transistor evolves from a partial gate to a gate‐all‐around structure. A 1D nature of the channel near the transistor threshold voltage is found to offset the limitations of the partial gate.

Cryogenic characteristics of UTBB SOI Schottky-Barrier MOSFETs

Schottky-Barrier (SB) MOSFETs are fabricated and characterized at room temperature (RT) and 5.4 K. The substrate bias impacts on SB MOSFETs are systematically investigated by measuring the threshold voltage Vth, subthreshold swing SS and transconductance Gm, showing the back gate has almost no effects on these parameters at 5.4 K, in contrast to the results measured at RT. Some oscillations are created in Gm curves by the quantization effect and resonant tunneling at 5.4 K. A large hysteresis is found by enhanced dynamic threshold operation at 72 K due to hot carriers and the presence of a Schottky barrier at the drain.

Analogue properties of junction-less strained dg-mosfet

This paper discusses an extensive investigation on the influence of work-function (WF) tuning on analogue properties of the n-type junction-less strained double-gate MOSFET. The investigation on the device has been conducted with fixed level of input parameters operating in saturation mode by taking the dependency of analogue properties on the WF tuning into account. Numerical simulation was performed using industrial-based process/device simulator, Silvaco TCAD tools. The simulation results revealed that analogue properties of the device such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd) and early voltage (VEA) exhibited an increase of ~17.4%, ~104.7%, 96% and 69.4% respectively as the WF is slightly minimized. However, the output impedance (ro), and intrinsic gain (AV) were deteriorated for ~58.4% and ~16.2% respectively as the WF is slightly minimized.

Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters

In this paper, DC and analog/RF figures of merit (FOMs) for different geometrical variations of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For each nanosheet, the thickness (NT) varied from 5 nm to 9 nm and width (NW) varied from 10 nm to 50 nm to analyze the performance variations with the device's geometry. It is observed that DC metrics like switching ratio, drain induced barrier lowering (DIBL), and subthreshold swing (SS) degrade with increment in geometry of NS. Moreover, the increment in analog/RF FOMs like transconductance (gm), output conductance (gds), cutoff frequency (fT), transconductance frequency product (TFP), and gain bandwidth product (GBW) is observed as the width and thickness are increase towards 50 nm and 9 nm, respectively. However, intrinsic gain, GFP, and GTFP deteriorate as the physical dimensions of the NSFET increase. On top of that, inverter and ring oscillator (RO) circuits are designed and the performance is demonstrated by varying width of the nanosheet. The circuit analysis is performed in Cadence Virtuoso tool by using look-up table based Verilog-A model. A decrement of 17.6% in the delay of the inverter is noticed when the width is increased from 10 nm to 50 nm. Also, it is observed that the static current of inverter is less than pA, which ensures less static power dissipation. Furthermore, an increment of 46.5% in fosc of 3-stage RO is observed as width increased to 50 nm. According to the various results analyses, NSFET is a promising device for high performance and high frequency analog/RF applications for sub-7-nm technology nodes.

Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node

This paper demonstrates the impact of temperature variation on vertically stacked junctionless nanosheet field effect transistor (JL-NSFET) concerning analog/RF performances using different gate lengths (Lg) along with high-k gate dielectrics. A comprehensive analysis of analog/RF performances like Transconductance (gm), Gate capacitance (Cgg), Gate to drain capacitance (Cgd), Output conductance (gds), Intrinsic gain (Av), Maximum oscillation frequency (fMAX), Gain Frequency Product (GFP), Cutoff frequency (fT) is carried out for the temperature range 77 K to 400 K. It is noticed that with the decrease in temperature from 400 K to 77 K, there is an improvement in AV, GFP, fT, and fMAX by an amount of ∼7.43%, ∼78.4%, ∼78.38%, ∼50.9% respectively. It is also found AV gets degraded with the downscaling of Lg from 16 nm to 8 nm. However, the same resulted in the improvement of RF performance. From detailed analysis, it is further observed that the usage of high-k gate dielectrics (k = 22) in JL-NSFET devices is not suitable due to the depreciation of analog/RF FOMs. Moreover interestingly, it is also noticed that the improvement in analog/RF performance (ΔFoM=FoM(T=400) − FoM(T=100)) resulted from lowering the temperature can further be improved by downscaling of Lg and by using low-k gate dielectric.

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length

In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15 nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (ION), off-current (IOFF), subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (Vea) and intrinsic gain (Av). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device.

Extended Gate to source overlap Heterojunction Vertical TFET: Design, analysis, and optimization with process parameter variations

This report highlights the simulated results of Extended gate to source overlap Heterojunction Vertical Tunnel field effect transistor (EGH-VTFET) for low-power and high-performance applications. To boost the DC as well as Analog/RF performance parameters, a novel heterojunction double gate Vertical TFET structure is reported by utilizing germanium as a source material and Si as a channel and drain material. Further, optimization of performance parameters is carried out on the basis of process parameter variations. In addition, a thorough analysis of both DC and Analog/RF performance is carried out for proposed EGH-VTFET device with optimization and without optimization. A wide range of figure of merits(FOM) such as on-current(Ion), current ratio (Ion/Ioff), total gate capacitance(Cgg), transconductance(gm), output conductance(gds), transconductance to current ratio(gm/Id), cut-off frequency(fT) and intrinsic gain(Av) have been analysed.

A unified 2-D model for nanowire junctionless accumulation and inversion mode MOSFET in quasi-ballistic regime

A unified 2-D continuous potential model for cylindrical nanowire junctionless accumulation mode (JAM) MOSFET and conventional inversion mode (IM) MOSFET has been presented in this manuscript. The 2-D Poisson’s equation in cylindrical coordinates is solved analytically with the help of the superposition principle and evanescent mode analysis of the Fourier-Bessel series is performed. Both free and depletion charges are considered in the 2-D Poisson’s equation. The model thus derived is continuous across different operation regimes (depletion and accumulation/inversion) with respect to VGS. Further, a threshold voltage model is also derived from the potential model and an expression of drain-induced barrier lowering (DIBL) is formulated. The short channel drain current model is derived from the potential-based charge model and quasi-ballistic transport velocity model. Furthermore, models for transconductance (gm) and output conductance (gd) is also formulated from the drain current model. A 3-D TCAD tool from CogendaTM has been used to numerically verify our proposed unified analytical model.

Thermal annealing behavior of InP-based HEMT damaged by proton irradiation

In this paper, the effects of thermal annealing on the radiated InP-based high electron mobility transistors (HEMTs) is investigated. Proton irradiation is performed with energy of 2 MeV and fluence of 5 × 1013 cm−2, and subsequently the thermal annealing experiments are carried out at 100 ℃ and 200 ℃. Both drain-source saturation current (Id,sat) and maximum transconductance (gm,max) of the radiated devices demonstrate a certain degree of recovery after annealing at 100 ℃ and 200 ℃. Id,sat and gm,max recover by the maximum values of 17.37 % and 13.66% for 10 min annealing at 100 ℃, and 12.65% and 14.54% for 5 min thermal annealing at 200 ℃. The main reason for the recovery about the DC characteristics are the restore of carrier concentration and mobility. Thermal annealing has enhanced the atoms vibration, which decreases the concentration of defects by recombination and weakens the lattice scattering by rearranging the lattice. In addition, this paper reveals that different annealing temperature and duration will have different effects on irradiated InP-based HEMTs.

Analysis ofDCandRFperformance of Al0.31Ga0.69N/Al0.1Ga0.9N/β‐Ga2O3double quantum wellHEMTon silicon carbide substrate

In this work, we present the DC and RF performance of LG 0.8 μm Al0.31Ga0.69N/Al0.1Ga0.9N/β-Ga2O3 based high-electron mobility transistors (HEMTs) on Silicon Carbide (SiC) substrate. The proposed heterostructure is investigated using numerical simulation and the simulation models are validated against experimental results. The proposed HEMT improves the drain current density due to double quantum well structure, elevated carrier mobility, and enhanced carrier confinement. The two-dimensional electron gas (2DEG) of 6 × 1012 cm−2 is obtained from the upper channel (Al0.31Ga0.69N/Al0.1Ga0.9N) and 2.8 × 1012 cm−2 of 2DEG is obtained from the lower channel (Al0.1Ga0.9N/β-Ga2O3). The rectangular gate HEMT with LG = 0.8 μm and LGD = 1 μm on SiC substrate showed a peak on-state drain current density (IDS) of 1.67 A/mm, 259 mS/mm of transconductance (gm), 377 V of off-state breakdown voltage (VBR), and FT/FMAX of 40/100 GHz. The HEMT with 0.5 μm length gate field plate device showed an excellent VBR of 536 V and FT/FMAX of 21/132 GHz. The high performance of the proposed Al0.31Ga0.69N/Al0.1Ga0.9N/β-Ga2O3 HEMTs indicates its potential for future RF and power electronics applications.