On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

Abstract

This paper presents a three dimensional (3-D) statistical simulation study of a 7 nm technology node SOI p-channel step-FinFET and compares with that of a conventional FinFET (c-FinFET). For the first time we have investigated the impact of various dimensional parameters like Gate Length (LG), Fin width (Wfin1 and Wfin2, Wfin = fixed), Fin height (Hfin1 and Hfin2, Hfin = fixed) and Fin-width ratio on the performance of c-FinFET and step-FinFET devices. These FinFET structures have been designed and simulated in Cogenda Visual TCAD under certain boundary conditions and the performance has been analyzed. The electrical parameters such as ON-current (ION), OFF-current (IOFF), Sub-threshold Swing (SS), Drain Induced Barrier Lowering (DIBL), threshold voltage (Vt) roll-off, Transconductance (gm) and Transconductance Generation Factor (TGF) are extracted. It is observed that short channel effects (SCEs) can be controlled by reducing Wfin1, decreasing major fin height (Hfin1) and increasing Gate length (LG) (14 nm to 20 nm). It is noticed that there is a significant improvement in ION/IOFF ratio from 1.01 × 104 to 1.41 × 105 with respect to increased channel length, SS of 76.68 mV/decade to 67.8 mV/decade and excellent DIBL of 55 mV/V in c-FinFET. For the proposed step-FinFET at LG = 16 nm there is improved DIBL of 85 mV/V compared to the c-FinFET, which can be further improved up to 64.63 mV/V by decreasing the Hfin1/Hfin2 ratio (4 to 0.25). The parametric analysis concludes that step-FinFET is more susceptible to SCEs in terms of DIBL, Vt roll-off as compared to the c-FinFET. This work considers LG = 16 nm for analysing the dimensional variation effect on both the devices. In contrast c-FinFET is more preferable than the proposed device at lower technology nodes.