Abstract
In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (ION/IOFF) = ~106 shows a higher level of electrostatic integrity. At 5 nm LG with optimized spacer dielectric the device exhibits ~5 orders of improvement in IOFF and the improvement is less than ~2 orders at 20 nm LG. Thus, from the result analysis, the spacer dielectrics are essential at lower LG for better performance. For continued scaling, the HfO2 spacer dielectric ensures high performance with the lowest downfall in ION with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si3N4 respectively. With SiO2, Si3N4, and HfO2 spacers the asymmetric spacer ensures an ION/IOFF of ~106 which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes.
Highlights
The use of stacked nanowire field-effect transistors (NW-FETs) as a scaling alternative for CMOS technology has been proposed [1]
Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = 64 mV/dec, drain induced barrier lowering (DIBL) = 45 mV/V, and switching ratio (ION/IOFF) = 106 shows a higher level of electrostatic integrity
Inner spacers are being used in NW-FETs, according to recent research [6]
Summary
The use of stacked nanowire field-effect transistors (NW-FETs) as a scaling alternative for CMOS technology has been proposed [1]. These spacers divide the gate stack between the nanowires and the highly doped source/drain regions. In critical VLSI system manufacturing [4], NW-FETs could be made in high yield, and nanosheet and NW thickness can be scaled down to sub-10 nm [5]. The need for a spacer between source and drain terminals is fundamental for sub-10 nm technology nodes to overcome SCEs. the introduction of spacer raises the series resistance between potentials terminals resulting in increased ION. The asymmetric spacer reduces direct tunneling between channel and drain and reduces the feedback miller capacitance effect.
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