A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement

Abstract

In this paper, we report, the hot carrier reliability issue in the Si1-xGex source/drain nanotube (NT) junctionless field-effect transistor (JLFET) with temperature variations. The surface potential, electric field and drain current have been formulated by developing a physics-based analytical model. SiGe in the source/drain regions creates valence band discontinuity of ΔEg = 0.23 eV which significantly increases the tunneling width at the channel/drain interface and therefore, results in a diminished L-BTBT action. The results demonstrate that at T = 500 K, drain current with the influence of interface trap charges in the Si1-xGex S/D architecture shows better immunity than the conventional NTJLFET. The Si1-xGex S/D enhances the reliability of analog/RF parameters such as transconductance (gm), intrinsic gain (gm/gd), cut-off frequency (fT), and gain-transconductance-frequency-product (GTFP), against the hot carriers. We have also explored the reliability with germanium (Ge) content, x and observed that for Ge content above x = 0.3, the reliability degrades in terms of higher electron temperature, reduced gm, and lower fT. The analytical results are verified and are in good agreement with results of Sentaurus TCAD simulations. The Si1–xGex S/D architecture combined with NT core gate can help relieve the HCI trap charge reliability for JLFETs leading to significantly improved analog/RF parameters.