An analytical model for P+ pocket SiC gate all around Junctionless field effect transistor with impact of high temperature

Abstract

In this article, we examined the influence of temperature in P+ pocket silicon carbide (SiC) gate all around junctionless field effect transistor (GAA JLFET). The inclusion of P+ pocket on source and drain side regions lead to an efficient volume depletion in JLFET. This results in increased tunneling width at channel-drain interface which reduced the L-BTBT induced OFF-state current of order to ∼10−15. It has been observed that using wide band gap material SiC as nanowire make the device temperature immune at higher drain voltages. A compact model with consideration of Poisson's equation for nanowire has been developed for surface potential (φi (r, z, T)), threshold voltage (Vth) and electric field (Ez) for P+ pocket SiC GAA JLFET. The P+ pocket has been considered while modeling the surface potential and electric field of SiC GAA JLFET. The presented compact model include the influence of temperature on surface potential and electric field as well. The performance of proposed compact model has been further validated with simulations results obtained from the SILVACO TCAD and it has shown the good agreement with simulation results.