Top-gate Thin-film Transistors Research Articles

Modeling and characterization of low frequency noise in self-aligned top-gate coplanar IGZO thin-film transistors

Abstract A modified low-frequency noise (LFN) model was proposed to accurately estimate the quality of the gate dielectric in self-aligned top-gate (SA TG) coplanar structure indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs). The proposed LFN model was derived by modifying the conventional carrier number with correlated mobility fluctuation model considering the peculiar characteristics of SA TG coplanar IGZO TFTs such as the channel length reduction due to the diffusion of hydrogen atoms or oxygen vacancies from the source/drain to the channel, as well as the relatively large source/drain parasitic resistance. The proposed model was validated by demonstrating that the measured LFN values were in good agreement with the predicted values from the proposed model for all SA TG coplanar IGZO TFTs with SiO2 gate dielectrics deposited under different plasma-enhanced chemical vapor deposition (PECVD) power densities. The near-interface gate dielectric trap densities extracted from each TFT using the proposed LFN model revealed a clear increase as the PECVD power increased, which is considered a major cause of poor positive-bias-temperature-stress stability of the SA TG coplanar IGZO TFT with SiO2 gate dielectric deposited under high PECVD power conditions.

Synergistic Effects of Deposition Temperatures for Active and Gate Insulator of Top-Gate Thin-Film Transistors Using InGaZnO Channels Prepared by Thermal Atomic-Layer Deposition

Synergistic Effects of Deposition Temperatures for Active and Gate Insulator of Top-Gate Thin-Film Transistors Using InGaZnO Channels Prepared by Thermal Atomic-Layer Deposition

Low-temperature preparation and characteristics of top-gate thin-film transistors with La-ZTO active layers and polymethylmethacrylate dielectric layers

A top-gate coplanar-structure thin-film transistor (TFT) combining the advantages of both a co-sputtered amorphous La-doped ZnSnO (a-La-ZTO) active layer and solution-based polymethylmethacrylate (PMMA) gate dielectric layer has been prepared under low temperature (100 °C) with low cost for the first time. The results indicate that the PMMA thin film demonstrates anti-reflection properties when it combines with a-La-ZTO layer to form a double-layer film, displaying high transparency to visible light of ∼90.3%. Moreover, it was found that the La target power during the deposition of a-La-ZTO film plays an important role in suppressing the formation of oxygen vacancies and adjusting the carrier concentration of a-La-ZTO active layer, thus impacting a-La-ZTO TFT performance. Overall, the optimum a-La-ZTO TFT with a La target power of 13.9 W, working in an n-channel enhancement mode, possesses a large saturated mobility (>10 cm2 (Vs)−1) and an on/off drain current ratio over 105.

High-performance ultrathin solution-processed SnO2 top-gate thin-film transistors by constructing high-quality dielectric/channel interface

In this work, we developed a low-thermal-budget approach to realize high-performance solution-processed oxide thin-film transistors (TFTs). To construct high-quality dielectric/channel interface, the corrosion-resistant SnO2 channel and further O2 plasma pre-treatment were adopted to minimize the problematic interface defects. With this strategy, the afforded solution-processed SnO2 TFTs exhibited improved electrical performance and stability, including a descent field-effect mobility (μFE) of 21.4 cm2/V·s, high on/off ratio (Ion/Ioff) of 109, positive threshold voltage (Vth) of 0.39 V, steep SS of 94.7 mV/dec, and small ΔVth of 0.08 and −0.03 V under PBS and NBS, respectively. This work demonstrates a promising fabrication approach for solution-processed oxide TFTs towards advanced applications.

High mobility of IGO/IGZO double-channel thin-film transistors by atomic layer deposition

In this paper, top-gate thin-film transistors (TFTs) of two stacked double-channel layers derived from atomic layer deposition in combination with the plasma-enhanced chemical vapor deposition (PECVD) process were fabricated. The Hall measurement shows that the Hall mobility of the indium gallium oxide (IGO)/indium gallium zinc oxide (IGZO) active layer is 1.6 times more that of the amorphous In-rich IGZO/IGZO layer due to superior carrier percolation conduction paths from the polycrystalline IGO layer. Furthermore, x-ray photoelectron spectroscopy analysis indicates that the IGO/IGZO film has much less oxygen vacancy concentration, which is advantageous in improving not only mobility but also stability. The optimized IGO/IGZO TFT showed both high mobility (38.0 cm2 V−1 s−1) and high stability (ΔVTH = +0.14 V) of a positive bias stress under post-deposition annealing at 250 °C. This strategy provides a feasible process for realizing high-performance TFTs that is compatible with ALD-derived oxides and commercial PECVD techniques in the industry.

Output breakdown characteristics of amorphous InGaZnO thin-film transistors at high gate voltage

Output characteristics of top-gate amorphous InGaZnO thin-film transistors are investigated at high gate voltage. With the increasing drain voltage, an output breakdown crops up closely following a drastic uprush of drain current. Such dramatically elevated drain current derives from the self-heating (SH) effect-generated channel donors. Measured at different high gate voltages, the output breakdown occurs in either linear or saturation regime, respectively, corresponding to normally-on and normally-off transfer curve, while the SH-triggering powers are almost identical. The conductor-like channel originates from the SH-induced high donor population, while the disconnection between channel and drain is caused by a highly defective region near drain, where the hot-carrier damage is violently activated by the SH-induced high temperature and the high drain electric field in saturation regime.

High mobility and productivity of flexible In2O3 thin-film transistors on polyimide substrates via atmospheric pressure spatial atomic layer deposition

We fabricate In2O3 films using atmospheric pressure spatial atomic layer deposition (AP S-ALD) and investigate their properties at various temperatures (150 °C–225 °C). As the temperature increased, the growth per cycle (GPC) increases, with the GPC and refractive index reaching values of 1.33 and 2.02, respectively, at 225 °C. The In2O3 thin film indicates a reduction in carrier concentration from 1.53 ± 1.37 × 1021 to 3.09 ± 0.53 × 1020 cm−3 as the temperature increased, and a decrease in the resistance from 3.55 ± 0.07 × 10−3 to 3.70 ± 0.01 × 10−4 Ω∙cm, which is attributed to a decrease in the impurity concentration (150 °C: 1.5 at.%; 175 °C: 1.0 at.%; 200 °C: N/A; 225 °C: N/A) and an increase in crystallinity. We use the In2O3 film as a channel layer in a top-gate bottom-contact thin-film transistor (TG-BC TFT). The device shows excellent performance characteristics, including a field-effect mobility of 69.8 cm2/V·s, a threshold voltage of −0.06 ± 0.22 V, and a subthreshold swing of 0.16 ± 0.01 V/decade. We successfully fabricated high-mobility TFTs and demonstrated their reliability via bias and 50,000 bending tests. The high-performance channel layer of the TFTs fabricated using AP S-ALD are promising for flexible applications.

Abnormal Threshold Voltage Shift and Sub-channel Generation in Top-Gate InGaZnO TFTs under Backlight Negative Bias Illumination Stress

Previous reports on the top-gate IGZO thin-film transistors (TFTs) under negative bias illumination stress (NBIS) show a threshold voltage (VTH) shift to the left. However, in the present study, a right shift in VTH was observed in the reverse-sweep current–voltage (I–V) curves after applying NBIS to top-gate IGZO TFTs by a UV backlight. The hysteresis window of the forward and reverse sweep I–V curves widened with the increase in the stress time. The abnormal VTH shift and hysteresis-window increment are explained using an energy-band diagram. In addition, an abnormal gm peak appeared in the forward I–V curve after 2000 s of the backlight NBIS, which was verified by testing the devices with different dimensions. Silvaco TCAD simulation results indicated a strong electric field in the sidewall, confirming the generation of sub-channels. The comparison of the ΔVTH after UV backlight NBIS in three different devices suggested that the higher N2O/SiH4 flow rate and lower power deposition can produce a good quality buffer layer. A rapid examination of a buffer layer is possible using the backlight NBIS. In addition, the presence of H2 in the buffer layer was confirmed by the thermal desorption spectroscopy. Finally, the reliability of the devices can be enhanced by improving the modulation of the existing deposition process.

Experiment study and analytical modeling of fully solution processed organic thin film transistors with conductive polymer top-gate electrode: Performance optimization

In this paper, various fully solution-processed top-gate bottom contacts organic thin-film transistors based on printed silver nanoparticles electrodes were fabricated, electrically characterized, and analytically modeled. The performance of the designed devices thermally and laser sintered nanoparticles electrodes was investigated. The device based on electrode sintered thermally exhibits improved contacts with an on/off ratio of 1.6 × 103 and a saturation mobility of 1.23 × 10−2 cm2V−1s−1. The current–voltage characteristics of OTFTs in terms of the transfer and output characteristics were also modeled and reproduced using an analytical model. Furthermore, various effects were considered in the used model, including the channel length modulation and contact resistance effects as well as field-effect mobility dependence of the gate voltage. The proposed model results for the devices were found to be in a good agreement with the experimental data in terms of the transfer and output characteristics. It was found that the used analytical model correctly describes the electrical characteristics, and it is proved to be accurate enough to explain the charge transport in these types of OTFTs. The development of such model will certainly help in the design of high-performance nanomaterials based OTFTs and their future advancement as well.

Organic/Inorganic Hybrid Top-Gate Transistors with Ultrahigh Electron Mobility via Enhanced Electron Pathways

The top-gate structure is currently adopted in various flat-panel displays because of its diverse advantages such as passivation from the external environment and process compatibility with industries. However, the mobility of the currently commercialized top-gate oxide thin-film transistors (TFTs) is insufficient to drive ultrahigh-resolution displays. Accordingly, this work suggests metal-capped Zn-Ba-Sn-O transistors with top-gate structures for inducing mobility-enhancing effects. The fabricated top-gate device contains para-xylylene (PPx), which is deposited by a low-temperature chemical vapor deposition (CVD) process, as a dielectric layer and exhibits excellent interfacial and dielectric properties. A technology computer-aided design (TCAD) device simulation reveals that the mobility enhancement in the Al-capped (Zn,Ba)SnO3 (ZBTO) TFT is attributed not only to the increase in the electron concentration, which is induced by band engineering due to the Al work function but also to the increased electron velocity due to the redistribution of the lateral electric field. As a result, the mobility of the Al-capped top-gate ZBTO device is 5 times higher (∼110 cm2/Vs) than that of the reference device. These results demonstrate the applicability of top-gate oxide TFTs with ultrahigh mobility in a wide range of applications, such as for high-resolution, large-area, and flexible displays.

A Light Shield Temperature Sensor for a Display Backplane

Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) display are operated by voltage or current driving. Several types of Thin-Film Transistor (TFT) are used in the backplane of a display, LTPS and a-IGZO TFTs are those. As the applied voltage increases to increase the brightness of the display, heat generation also increases at the channel of the TFT. Such heat generation increase the temperature, which degrades the characteristics of the TFT, and decrease the lifetime of the organic device. Therefore, in order to keep the quality of the display, it is necessary to monitor the temperature of the display and control related signals to implement optimal image quality. There are various temperature sensors which can be used to detect such a temperature change in a display. In the case of using a discrete temperature sensor, the process and cost are increased by attaching the temperature sensor additionally. However, in the case of a temperature sensor integrated into the display, an process for the temperature sensor is not necessary. One way to integrate is using resistance changing material with a reference resistor outside. In this case, temperature accuracy can be reduced when the reference resistance changes due to the influence of the external temperature. To solve the problem, external reference resistance is removed in this proposed sensor scheme. Figure 1 shows the developed thin-film temperature sensor, which consists of two wires connected in series. The temperature coefficients of Molybdenum (Mo) and Indium Tin Oxide (ITO) are different from each other, and that of ITO is about 1.2 times or more than that of Mo. In this scheme, no external resistance is required. In addition, to reduce the process steps, a thin film temperature sensor is designed to replace a light shield layer which is formed at the bottom of the active layer to prevent the input of light. The two thin film materials are connected in series and the voltages at a connecting point are measured. The generated heat transferred to the temperature sensor was tested for repeatability and accuracy. The thin-film temperature sensor was designed to be located at the bottom of a-IGZO Top Gate TFT structure to check the heating during the operation of TFT. an interlayer insulation film was deposited on the temperature sensor before deposition of the active layer. The temperature of the TFT was measured by a temperature sensor Figure 1. shows the schematic cross-sectional structure of the developed oxide TFT with an integrated temperature sensor. Figure 1

Trench-Structured High-Current-Driving Aluminum-Doped Indium–Tin–Zinc Oxide Semiconductor Thin-Film Transistor

This letter presents a thin-film transistor architecture, in which a “trench” is introduced between the source and drain electrode to enhance current flow. The top-gate top-contact oxide Trench thin-film transistor has a superior on-current per width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$27.7~\mu \text{A}/ \mu \text{m}$ </tex-math></inline-formula> at a drain voltage of 4.1 V. It also has a good subthreshold swing of 0.122 V/dec and turn-on voltage of −0.4 V. This study explores the operating mechanism of the high-current-driving Trench oxide thin-film transistor.

Physics-Based Compact Model of Current Stress-Induced Threshold Voltage Shift in Top-Gate Self-Aligned Amorphous InGaZnO Thin-Film Transistors

Threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text{T}}$ </tex-math></inline-formula> ) under various current stress (CS) conditions need to be quantitatively studied in self-aligned top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Here, we propose a stretched-exponential function (SEF)-based <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text{T}}$ </tex-math></inline-formula> model that can be applied to various combinations of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{DS}}$ </tex-math></inline-formula> . The proposed model indicates the characteristic electron trapping time constant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau _{1}$ </tex-math></inline-formula> is inversely proportional to ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}} - {V}_{\text{T}}$ </tex-math></inline-formula> ). In contrast, the time constant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau _{2}$ </tex-math></inline-formula> is directly proportional to the square root of ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{DS}}+{V}_{\text{bi}}$ </tex-math></inline-formula> ), presumably due to the local donor creation by a lateral electric field. The proposed model was verified experimentally in various <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{DS}}$ </tex-math></inline-formula> configurations. Further, it is confirmed that the lateral electric field dominantly influences donor creation near the drain.

The Fabrication of Indium–Gallium–Zinc Oxide Sputtering Targets with Various Gallium Contents and Their Applications to Top-Gate Thin-Film Transistors

We prepared amorphous indium–gallium–zinc oxide (a-IGZO) thin films with various Ga content ratios and investigated their feasibility as the active channel layers of top-gate thin-film transistors (TFT). First, the 2-inch IGZO sputtering targets with stoichiometric ratios of InGaZn2O5, InGaZnO4, and InGa2ZnO5.5 were fabricated using In2O3, Ga2O3, and ZnO oxide powders as raw materials via sintering treatments at temperatures ranging from 900 °C to 1300 °C for 6 h or 8 h. X-ray diffraction analysis indicated that the InGaZn2O5 and InGaZnO4 targets are single-phase structures whereas the InGa2ZnO5.5 target is a two-phase structure. Hall effect measurement indicated that the a-InGaZn2O5 and a-InGaZnO4 layers possess a carrier concentration (N) of about 1019 cm−3 and a resistivity (ρ) of about 10−2 Ω·cm; however, the N of the a-InGa2ZnO5.5 layer is only 1017 cm−3, and the ρ is about 1 to 4 Ω·cm. Moreover, the a-InGaZn2O5 layer exhibited the highest Hall-effect mobility (μHall) of 21.17 cm2·V−1·sec−1. This indicated that the impedance of Ga3+ ions to carrier migration is the main factor affecting the electrical properties of a-IGZO layers. Ga content in the a-IGZO channel similarly affects the performance of the TFT devices prepared in this study. The annealing at 300 °C for 1 h in an ambient atmosphere was found to significantly improve the electrical properties of the TFT devices. The best performance was observed in the a-InGaZnO4 TFT sample subjected to post-annealing at 300 °C with Vth = −0.85 V, μFE = 8.46 cm2, V−1·sec−1, SS = 2.31, V·decade−1, and Ion/Ioff = 2.9 × 104.

Reactively-sputtered AlOx passivation layer for self-aligned top-gate amorphous InGaZnO thin-film transistors

The direct-current reactive sputtering of aluminum oxide (AlOx) films with Al target was investigated to provide a preferable passivation layer (PL) for self-aligned top-gate (SATG) amorphous metal oxide semiconductor (AOS) like amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). The grown AlOx films exhibited excellent electrical characteristics, with major parameters including a relative dielectric constant around 9, breakdown electric field of 3.7 MV/cm, and leakage current of 6.29 × 10−8 A/cm2 at 2 MV/cm. It is shown that the AlOx PL, together with a PECVD SiO2 interlayer could provide SATG a-IGZO TFTs with trustworthy environmental and electrical stability.

Remarkable Stability Improvement with a High‐Performance PEALD‐IZO/IGZO Top‐Gate Thin‐Film Transistor via Modulating Dual‐Channel Effects

AbstractPlasma‐enhanced atomic layer deposition (PEALD)‐based bilayer IZO (back channel)/IGZO top‐gate thin‐film transistors (TFTs) with different IZO and IGZO layer thicknesses are fabricated to evaluate the correlation between thickness and electrical characteristics/reliability caused by dual‐channel modulation. The dual‐channel formed by IZO stacked on the backchannel improves both mobility and reliability of devices as the IZO layer thickness increases. In the TCAD simulation, as the thickness of IZO increases, the current flowing through the IZO channel among the dual channels increases and the main channel transition from IGZO to IZO occurs above a certain IZO layer thickness. The main channel transition to IZO, which has high mobility and is located in the backchannel away from the gate insulator (GI), leads to a mobility increase with a lower threshold voltage (Vth) shift and a remarkable improvement of reliability deteriorated by the GI. As a result, PEALD‐based IZO/IGZO TG TFTs exhibit both high mobility (≈40 cm2 V−1 s−1) and high stability (ΔVth = ‐0.07 V) of a positive bias temperature stress up to 10 800 s. This suggests that ALD‐based dual‐channel regulation by nanoscale thickness control of the stacking oxide semiconductor can overcome the trade‐off between mobility and reliability.

Cation Composition-Dependent Device Performance and Positive Bias Instability of Self-Aligned Oxide Semiconductor Thin-Film Transistors: Including Oxygen and Hydrogen Effect.

Amorphous oxide semiconductor transistors control the illuminance of pixels in an ecosystem of displays from large-screen TVs to wearable devices. To satisfy application-specific requirements, oxide semiconductor transistors of various cation compositions have been explored. However, a comprehensive study has not been carried out where the influence of cation composition, oxygen, and hydrogen on device characteristics and stability is systematically quantified, using commercial-grade process technology. In this study, we fabricate self-aligned top-gate structure thin-film transistors with three oxide semiconductor materials, InGaZnO (In/Ga/Zn = 1:1:1), In-rich InGaZnO, and InZnO, having mobility values of 10, 27, and 40 cm2/V·s, respectively. Combinations of varied amounts of oxygen and hydrogen are incorporated into each transistor by controlling the fabrication process to study the effect of these gaseous elements on the physical nature of the channel material. Electrons can be captured by peroxy linkage (O22-) or undercoordinated In (In* to become In+), which are manifested in the extracted subgap density-of-states profile and first-principles calculations. Energy difference between electron-trapped In+ and O22- σ* is the smallest for IGZO, and In+-O22- annihilation occurs by electron excitation from the subgap In+ state to the O22- σ*. Furthermore, characteristic time constants during positive bias stress and recovery reveal the various microscopic physical phenomena within the transistor structure between different cation compositions.

Chemically Tunable Organic Dielectric Layer on an Oxide TFT: Poly(p-xylylene) Derivatives.

Inorganic materials such as SiOx and SiNx are commonly used as dielectric layers in thin-film transistors (TFTs), but recent advancements in TFT devices, such as inclusion in flexible electronics, require the development of novel types of dielectric layers. In this study, CVD-deposited poly(p-xylylene) (PPx)-based polymers were evaluated as alternative dielectric layers. CVD-deposited PPx can produce thin, conformal, and pinhole-free polymer layers on various surfaces, including oxides and metals, without interfacial defects. Three types of commercial polymers were successfully deposited on various substrates and exhibited stable dielectric properties under frequency and voltage sweeps. Additionally, TFTs with PPx as a dielectric material and an oxide semiconductor exhibited excellent device performance; a mobility as high as 22.72 cm2/(V s), which is the highest value among organic gate dielectric TFTs, to the best of our knowledge. Because of the low-temperature deposition process and its unprecedented mechanical flexibility, TFTs with CVD-deposited PPx were successfully fabricated on a flexible plastic substrate, exhibiting excellent durability over 10000 bending cycles. Finally, a custom-synthesized functionalized PPx was introduced into top-gated TFTs, demonstrating the possibility for expanding this concept to a wide range of chemistries with tunable gate dielectric layers.

Reduction of leakage current in amorphous Oxide-Semiconductor Top-gated thin film transistors by interface engineering with dipolar Self-Assembled monolayers

Top gate (TG) thin film transistors (TFTs) featuring amorphous metal oxide semiconductors (a-MOS), such as indium-gallium-zinc-oxide (IGZO), bear a great potential for large-area flexible and transparent electronics. The fabrication costs of these devices can be noticeably reduced by introduction of solution processes instead of standard fabrication routes involving vacuum deposition and complicate photolithography. However, solution-processed TG a-MOS TFT often causes considerable gate leakage in comparison with vacuum-processed device. In this context, we present a simple and straightforward approach to reduce the gate leakage of IGZO-based TG TFTs, which predominantly involves solution-based procedures. We engineer the IGZO/insulator interface by dipolar, silane-anchored self-assembled monolayers (SAMs) providing a favorable built-in electric field to reduce the leakage current in TFTs. The parameter correlates well with the direction and value of the molecular dipole moment defined by either electron accepting or electron donating character of the terminal tail group. These SAMs, prepared by spin-coating procedure, were characterized in detail by a combination of several complementary experimental techniques, providing also a useful background information for the device experiments.

Short-Channel Top-Gate InGaZnO Thin-Film Transistors Fabricated With Boron Implantation Into Source/Drain Regions

In this brief, we discuss top-gate InGaZnO thin-film transistors (InGaZnO TFTs) fabricated with boron (B) implantation into the source–drain regions, focusing on channel shortening. B was implanted through the gate insulator into the InGaZnO layer. From scanning capacitance microscopy (SCM) analysis, we found that boron implantation in the S/D regions of InGaZnO TFTs induces channel shortening. We also found that such channel shortening is suppressed by optimizing acceleration voltage in the boron implantation process, leading to good operation in short-channel ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5~\mu \text{m}$ </tex-math></inline-formula> ) InGaZnO TFT.