Reduction of leakage current in amorphous Oxide-Semiconductor Top-gated thin film transistors by interface engineering with dipolar Self-Assembled monolayers

Abstract

Top gate (TG) thin film transistors (TFTs) featuring amorphous metal oxide semiconductors (a-MOS), such as indium-gallium-zinc-oxide (IGZO), bear a great potential for large-area flexible and transparent electronics. The fabrication costs of these devices can be noticeably reduced by introduction of solution processes instead of standard fabrication routes involving vacuum deposition and complicate photolithography. However, solution-processed TG a-MOS TFT often causes considerable gate leakage in comparison with vacuum-processed device. In this context, we present a simple and straightforward approach to reduce the gate leakage of IGZO-based TG TFTs, which predominantly involves solution-based procedures. We engineer the IGZO/insulator interface by dipolar, silane-anchored self-assembled monolayers (SAMs) providing a favorable built-in electric field to reduce the leakage current in TFTs. The parameter correlates well with the direction and value of the molecular dipole moment defined by either electron accepting or electron donating character of the terminal tail group. These SAMs, prepared by spin-coating procedure, were characterized in detail by a combination of several complementary experimental techniques, providing also a useful background information for the device experiments.