Top-gate Thin-film Transistors Research Articles

Dip-coated Al–In–Zn–O thin-film transistor with poly-methylmethacrylate gate dielectric

Top-gate thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) as channel layer and organic polymethylmethacrylate (PMMA) as dielectric layer were prepared via a solution process of dip coating method. The additive Al led to the band gap of AIZO films wider and effectively controlled the oxygen vacancies. This behaviour indicates that Al acted as an effective carrier suppressor in the IZO materials. Moreover, it was found that organic PMMA dielectric layer exhibited antireflection effect when it combined with a-AIZO film to form double-layer structure, showing the highly transparent of ∼94.7%. The a-AIZO-TFT with Al atomic content of 30% exhibited optimum device characteristics, with a high saturated mobility of 26.8 cm2 V−1 s−1, a small subthreshold swing of 0.24 V/decade, and slight hysteresis with Vth shift of ∼−1.26 V.

μc-Si thin film transistors with very thin active layer

N-type microcrystalline silicon (μc-Si) top-gate Thin Film Transistors (TFTs) are fabricated at a maximum temperature of 180°C using different thicknesses of undoped μc-Si active layers. The effect of the thickness on the TFT performance is experimentally studied and then modeled using Silvaco software tools. The experimental high improvement of the subthreshold swing and the limitation of the rear channel effect, when using very thin active layer, are shown to be due to the increase of the lateral electrical field between the source or drain and the active layer. This increase of the lateral field is shown to be much more important for defected active layer as the microcrystalline silicon one compared to single crystalline silicon active layer. The importance of the use of very thin active layer for amorphous or ploy–micro–nano-crystalline silicon based TFTs is then demonstrated.

Fabrication and Characteristics of the Nano-Polysilicon Thin Film Transistors

In this paper, we report the fabrication and characteristics of the top-gated thin film transistors (TFTs) with nanopolysilicon as active layers. The nanopolysilicon thin films were deposited on SiO2 layers by LPCVD and the SiO2 layers were grown on the single silicon substrates. Then the nanopolysilicon thin film transistors with different thin film thicknesses and different channel width length radios were fabricated by CMOS technology, in which the thicknesses of channel layers were 90nm and 120nm, and the channel width length radios were 160μm/160μm, 320μm/160μm and 640μm/160μm, respectively. The experiment results show that drain current is in proportion to channel width length radio. In addition, when the thickness of the nanopolysilicon thin film is 90nm and the channel width length radio is 640μm/160μm, the on/off current radio reaches 106.

Effect of active layer thickness on device performance of a-LZTO thin-film transistors

The dependence of the electrical properties of amorphous lanthanum–zinc–tin–oxides (a-LZTOs)-based top-gate thin-film transistors (TFTs) on active layer thicknesses (dT) is investigated. It is found that the on-to-off current ratio (Ion/off) of TFT improved with the thickness of LZTO active layer decreased from 84nm to 32nm, whereas the saturation mobility and the subthreshold swing of device degraded. The improvement in Ion/off is attributed to the decrease in off-current of TFT due to an increase in resistance of the very thin LZTO film. Moreover, the deterioration in properties of device with the thin active layer is associated with the trap states incorporated in TFT and interface scattering effect.

All-brush-painted top-gate organic thin-film transistors

Brush painting, a simple and fast solution processing technique, possesses promising multiple applications in ultra-low-cost organic electronics with large-area manufacture. Benefiting from effective brush painting of high quality conductive electrodes, semiconductive layers and dielectric layers, all-brush-painted top-gate transistors were successfully constructed with a maximum mobility of 0.14 cm2 V−1 s−1.

Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate

A multigate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) is a recently popular topic in the field of Si devices. In this study, self-aligned planar metal double-gate poly-Si TFTs consisting of an embedded bottom metal gate, a top metal gate fabricated by a self-alignment process, and a lateral poly-Si film with a grain size greater than 2µm were fabricated on a glass substrate at 550°C. The nominal field-effect mobility of an n-channel TFT is 530cm2/Vs, and its subthreshold slope is 140mV/dec. The performance of the proposed TFTs is superior to that of top-gate TFTs fabricated using equivalent processes.

Thin film transistors based on zinc nitride as a channel layer for optoelectronic devices

Zinc nitride films were used as an active layer in thin film transistors to assess its performance in optoelectronic applications. Those nitride layers were grown by radio-frequency magnetron sputtering in Ar/N2 ambient using a Zn target. Bottom- and top-gate thin film transistors were fabricated by photolithography processes. Transmission measurements for these particular layers showed an absorption edge around 1.3 eV. Normally off transistor characteristics with a threshold voltage of 6 V were obtained in the bottom-gate configuration without post-growth annealing. In the saturation region, those transistors produced enhanced output characteristics under illumination with infrared/visible light.

High-performance vertically stacked bottom-gate and top-gate polycrystalline silicon thin-film transistors for three-dimensional integrated circuits

The three-dimensional CMOS inverter with top-gate (TG) poly-Si thin film transistors (TFTs) vertically stacked on the bottom-gate (BG) poly-Si TFTs have been proposed to achieve high-performance characteristics via excimer laser crystallization (ELC) for the first time. Under an appropriate laser irradiation energy density, the silicon grain growth could be controlled from the sidewalls of the bottom-gate structure and thus the high-quality laterally grown poly-Si film with single perpendicular grain boundary in the channel would be formed for the BG TFTs. In addition, a simple ELC method was also utilized to the top-layered poly-Si film for TG TFTs as compared with solid-state-crystallized (SPC) ones. As a result, the field-effect mobilities of the proposed n-type BG and p-type TG TFTs could be significantly increased to be 390 and 131cm2/Vs, respectively, in contrast to 32.3 and 14.7cm2/Vs for the SPC ones, accordingly. Furthermore, such three-dimensional (3-D) TFT have also been employed to demonstrate the inverter devices and is suitable for future 3-D ICs as well as system-on-panel applications.

Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

Bias instability of top-gate amorphous-indium–gallium–zinc-oxide thin-film transistors with source- and drain-offsets is reported. Positive and negative gate bias-stress (VG_STRESS) respectively induce reversible negative threshold-voltage shift (ΔVTH) and reduction in on-current. Migration of positive charges towards the offsets lowers the local resistance of the offsets, resulting in the abnormal negative ΔVTH under positive VG_STRESS. The reduction in on-current under negative VG_STRESS is due to increase in resistance of the offsets when positive charges migrate away from the offsets. Appropriate drain and source bias-stresses applied simultaneously with VG_STRESS either suppress or enhance the instability, verifying lateral ion migration to be the instability mechanism.

Energy band engineering and controlled p-type conductivity of CuAlO2 thin films by nonisovalent Cu-O alloying

The electronic band structure and p-type conductivity of CuAlO2 films were modified via synergistic effects of energy band offset and partial substitution of less-dispersive Cu+ 3d10 with Cu2+ 3d9 orbitals in the valence band maximum by alloying nonisovalent Cu-O with CuAlO2 host. The Cu-O/CuAlO2 alloying films show excellent electronic properties with tunable wide direct bandgaps (∼3.46–3.87 eV); Hall measurements verify the highest hole mobilities (∼11.3–39.5 cm2/Vs) achieved thus far for CuAlO2 thin films and crystals. Top-gate thin film transistors constructed on p-CuAlO2 films were presented, and the devices showed pronounced performance with Ion/Ioff of ∼8.0 × 102 and field effect mobility of 0.97 cm2/Vs.

Top-gate thin-film transistors based on GaN channel layer

Gallium nitride (GaN) thin films were utilized as active channel layer to produce top-gate n-type thin-film transistors (TFTs). GaN thin films with wurtzite structure were deposited by reactive DC magnetron sputtering technique at room temperature using liquid gallium target. The GaN TFTs exhibit good electrical performance such as field effect mobility of 1 cm2/Vs, threshold voltage of −0.4 V, on/off current ratio of 105, and subthreshold swing of 0.8 V/decade.

Self-Aligned Top-Gate Oxide Thin-Film Transistor Formed by Aluminum Reaction Method

We developed a novel highly reliable self-aligned top-gate oxide semiconductor thin-film transistor (TFT) formed by the aluminum (Al) reaction method. In this method, Al diffusion into the oxide semiconductor was observed. The low sheet resistivity of the source/drain regions was attributed to Al working as a donor in the oxide semiconductor. The TFTs with 4 µm channel length exhibited a field-effect mobility of 9.8 cm2 V-1 s-1, a threshold voltage of -1.5 V, and a subthreshold swing of 0.22 V/decade. Highly reliable TFTs were obtained after 300 °C annealing without increasing the sheet resistivity of source/drain regions.

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In–Ga–Zn–O as the n-channel active layer and SiO 2 as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO 2 with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm 2/V s, the I on/ I off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.

High mobility top-gate and dual-gate polymer thin-film transistors based on diketopyrrolopyrrole-naphthalene copolymer

In this letter, the performance characteristics of top-gate and dual-gate thin-film transistors (TFTs) with active semiconductor layers consisting of diketopyrrolopyrrole-naphthalene copolymer are described. Optimized top-gate TFTs possess mobilities of up to 1 cm2/V s with low contact resistance and reduced hysteresis in air. Dual-gate devices possess higher drive currents as well as improved subthreshold and above threshold characteristics compared to single-gate devices. We also describe the reasons that dual-gate devices result in improved performance. The good stability of this polymer combined with their promising electrical properties make this material a very promising semiconductor for printable electronics.

High-performance and room-temperature-processed nanofloating gate memory devices based on top-gate transparent thin-film transistors

Transparent nanofloating gate memory devices based on top-gate zinc oxide thin-film transistors were developed. The proposed devices contained a facile and dry-synthesized palladium nanocluster array as a charge-trapping layer. The good programmable memory characteristics were exhibited due to the thin tunneling oxide, caused by the top-gate structure. The good endurance, data retention capability, and environmental stability demonstrated by the proposed device made it suitable for nonvolatile memory applications. As the whole processes were carried at room temperature, this letter has a potential use in fabricating high-performance and high-reliability nonvolatile memory devices on flexible substrates.

Electrical properties of top-gate oxide thin-film transistors with double-channel layers

Using ZnO, and three compositional In 2O 3-Ga 2O 3-ZnO (IGZO, In:Ga:Zn=1:1:1, 2:1:2, 2:2:1, atomic ratio) semiconductors, we have made and evaluated several double layered oxide thin-film transistors (TFTs). The drain current was mainly affected by the nearer channel material to a gate insulator. From the positive bias stress (PBS) tests, however, the electrical stability showed a complicated result, depending on both channel structures and post-heat treatments.

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO 2) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO 2 films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm 2/V-s; an on/off current ratio of 1 × 10 5; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage ( V th ) of 2.86 V.

Low-voltage-operated top-gate polymer thin-film transistors with high-capacitance P(VDF-TrFE)/PVDF-blended dielectrics

We report a poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)]/poly(vinylidene fluoride) (PVDF)-blended film as a high-capacitance polymer-gate dielectric layer for a low-voltage-operated top-gate organic field-effect transistor (OFET). OFETs with poly(9,9-dioctylfuorene- co-bithiophene) (F8T2) as an active layer exhibited a low operation gate voltage of less than 10 V with a reasonable field-effect mobility of 10 −4 cm 2/V for amorphous conjugated polymers. The operation voltage effectively decreased because of the high permittivity of the P(VDF-TrFE)/(PVDF)- blended film ( ε = 10.2). The remnant polarization disappeared completely; further, the hysteresis in the transfer plots induced by the ferroelectric P(VDF-TrFE) was effectively minimized by the disruption of a crystalline β-phase in the film via an increase in the blend ratio of PVDF.

(Invited) Nanocrystalline Silicon Thin Film Transistors

We review performance characteristics of top- and bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs). Top gate TFTs with nc-Si active layer of nearly 80% crystallinity along with a silicon oxide gate dielectric produce high electron mobilities; values two orders higher than the amorphous silicon counterpart. In contrast, bottom-gate TFTs with silicon nitride gate dielectric and nc-Si active layer of similar crystallinity yield a mobility that is only marginally better than amorphous silicon TFT. However, they are highly stable with no visible presence of defect state creation in the active layer. In contrast, top-gate TFTs suffer from severe charge trapping in the low quality oxide gate dielectric.

Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication

We developed self-aligned imprint lithography (SAIL) for top-gate amorphous silicon (a-Si) thin-film transistors (TFTs). Our SAIL process enables a device pattern definition in a single imprint step that uses a three-level mold. The various levels of the mold are defined by a stepwise opening of a chromium hardmask and subsequent dry-etching. For TFT fabrication we imprint, and consecutively etch the imprint resist levels and device layers. The imprinted top-gate a-Si TFTs have nickel silicide source/drain self-aligned to the gate with mobilities of ∼0.4 cm2/V s.