Top-gate Thin-film Transistors Research Articles

Effect of Electrode Materials on the Electrical Characteristics of Amorphous Indium-Tin-Gallium-Zinc Oxide Thin-Film Transistors.

In this study, we investigated the effect of electrode materials on the electrical characteristics of coplanar top-gate a-ITGZO thin-film transistors, in which the gate, source, and drain electrodes were made of the same metal, Ti or Al. The field-effect mobilities of the a-ITGZO thin-film transistors with Ti and Al electrodes were 35.2 and 20.1 cm²/V·s, respectively, and the threshold voltage of the a-ITGZO thin-film transistor with Ti electrodes was -0.4 V, whereas that of the transistor with Al electrodes was -1.8; this shift is attributed to the fact that Ti has a higher work function than Al. When Ti was used as the source and drain electrode material, the channel resistance and effective channel length were reduced owing to the penetration of metal atoms into the channel region from the edge of the source/drain electrodes.

Numerical Design of Carrier Transporting Layer in Top-Gate InGaZnO Thin-Film Transistors for Controlling Potential Energy.

Top-gate amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are designed with numerical analysis to control their electron potential energy. Design simulations show the effects of structural design on the electrical characteristics of these TFTs. In particular, the thicknesses of the channel (tch) and conducting (tc) layers, which play vital roles in TFT electrical performance, are varied from 1 to 50 nm to investigate the effect of thicknesses on the electron potential energies of the channel region and the electrode-semiconductor interfaces. The potential energies are precisely optimized for efficient charge transport, injection, and extraction, thus enhancing the electrical performance of these devices. It is also demonstrated that tch mainly affects mobility and threshold voltage, while tc mainly affects on-current. An acceptable threshold voltage of 0.55 V and high mobility of 14.7 cm²V-1s-1 are obtained with a tch of 30 nm and tc of 10 nm. Controllability of the electron potential energies and electrical performance of IGZO TFTs by means of structural design will contribute to realization of next-generation displays that have large areas and high resolutions.

Formulation and characterization of screen printable dopant ink for fabrication of polysilicon TFTs

To move the promise of printed electronics from the laboratory to volume production required adopting a new approach eliminating ink-jet printing and adopting instead a hybrid mature print and conventional process. Novel screen printable N+ and P+ dopant inks were developed to fabricate polysilicon thin film transistors (TFTs). Semiconductor-grade dopant inks were formulated from a combination of thermoset plastic with boron and phosphor compounds. Inks were screen printed on polysilicon active islands on a 300 mm square stainless-steel foil substrate. The drain and source of the top gate TFTs were then formed via a thermal anneal activation. The residue after annealing was removed with an inoffensive process to avoid damage to the thin silicon layer and gate oxide. Doping was uniform across 300 mm sheet substrate. The sheet resistance was modulated to 200 Ω sq−1 for the N+ and 1000 Ω sq−1 for the P+ active layer. Field mobility of polysilicon TFTs fabricated using this screen-printed dopant process were 80 cm2V s−1 for PMOS and 200 cm2V s−1 for NMOS using low-cost, mature equipment, and an easily manageable process that is both scalable and compatible with roll-to-roll manufacturing.

Optimization of Two-Dimensional Channel Thickness in Nanometer-Thick SnO2-Based Top-Gated Thin-Film Transistors Using Electric Field Thermopower Modulation: Implications for Flat-Panel Displays

Transparent amorphous oxide semiconductor (TAOS) based thin-film transistors (TFTs) are essential as the backplane for developing advanced flat panel displays. Among many TAOSs, amorphous (a-) SnO2...

Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric.

For high-speed and large-area active-matrix displays, metal-oxide thin-film transistors (TFTs) with high field-effect mobility, stability, and good uniformity are essential. Moreover, reducing the RC delay is also important to achieve high-speed operation, which is induced by the parasitic capacitance formed between the source/drain (S/D) and the gate electrodes. From this perspective, self-aligned top-gate oxide TFTs can provide advantages such as a low parasitic capacitance for high-speed displays due to minimized overlap between the S/D and the gate electrodes. Here, we demonstrate self-aligned top-gate oxide TFTs using a solution-processed indium-gallium-zinc-oxide (IGZO) channel and crosslinked poly(4-vinylphenol) (PVP) gate dielectric layers. By applying a selective Ar plasma treatment on the IGZO channel, low-resistance IGZO regions could be formed, having a sheet resistance value of ~20.6 kΩ/sq., which can act as the homojunction S/D contacts in the top-gate IGZO TFTs. The fabricated self-aligned top-gate IGZO TFTs exhibited a field-effect mobility of 3.93 cm2/Vs and on/off ratio of ~106, which are comparable to those fabricated using a bottom-gate structure. Furthermore, we also demonstrated self-aligned top-gate TFTs using electrospun indium-gallium-oxide (IGO) nanowires (NWs) as a channel layer. The IGO NW TFTs exhibited a field-effect mobility of 0.03 cm2/Vs and an on/off ratio of >105. The results demonstrate that the Ar plasma treatment for S/D contact formation and the solution-processed PVP gate dielectric can be implemented in realizing self-aligned top-gate oxide TFTs.

High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer.

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (μFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, μFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2. The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2/SnO2 interfaces to increase the mobility. Such high μFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

Channel-protecting fabrication of top-gate MoS2 transistor arrays

The surface passivation on MoS2 and other transition metal dichalcogenides (TMDs) has been widely studied and utilized to prevent contamination and oxygen/water vapor penetration. Such approaches are mostly applied on the back-gate transistors after the formation of source/drain electrodes, while the compatibility in constructing top-gate devices has not yet been experimentally explored. Here, based on the large-area MoS2 thin film prepared with the atomic layer deposition technique, we developed an experimental routine to fabricate top-gate MoS2 thin-film transistor arrays with the TMD channel protected by high-k dielectric during the entire device fabrication process. The channel protection is enabled by the high-quality Al2O3 dielectric with proper pretreatment. The transistors in the array have shown enhanced electrical performance compared to the non-protected devices. Such a robust and well-controlled fabrication technique is a typical case of developing functional electronic devices by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth, which can be further extended to the wide application in higher-level systems based on TMD materials.

Impact of Gate Size on Abnormal Current Rise Under an Electric Field in Organic Thin-Film Transistors

This article investigates the effects of different gate sizes on the electrical characteristics of top-gate organic thin-film transistors. During electrical measurements, an abnormal phenomenon is observed. For a fixed channel length, the current increases with the increasing gate length. In narrow-gate channel devices, gates are used to control carriers of low current density through the side channel area. However, the wide-gate length devices can effectively reduce contact resistance and control large side channels. In this article, integrated systems engineering–technology computer-aided design (ISE-TCAD) simulations were performed for this device containing an active layer with gate cladding. The strength of the electric field extended to the surrounding channel, and the active layer was affected by the cross-wall electric field. The ON-current, under the action of the electric field, improved as the current density of the side channel increased.

Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors

This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.

Contact Properties between Low-Resistive Al-Based Source/Drain and InO<sub>x </sub>in Top-Gate Bottom-Contact Oxide Thin-Film Transistor for Application to the Vertical-TFT

Contact Properties between Low-Resistive Al-Based Source/Drain and InO<sub>x </sub>in Top-Gate Bottom-Contact Oxide Thin-Film Transistor for Application to the Vertical-TFT

Contact Properties between Low-Resistive Al-Based Source/Drain and InO<sub>x </sub>in Top-Gate Bottom-Contact Oxide Thin-Film Transistor for Application to the Vertical-TFT

Contact Properties between Low-Resistive Al-Based Source/Drain and InO<sub>x </sub>in Top-Gate Bottom-Contact Oxide Thin-Film Transistor for Application to the Vertical-TFT

Stability of pentacene-based top gate thin film transistor with thick parylene as dielectric under humid environment

This study presents the influence of humidity effect in top gate transistors using pentacene as active layer. The devices are made on a planarized kapton substrate, and 1 μm thick parylene has been used both as gate dielectric and encapsulating layer. Two series of measurement conditions have been used. First, the humidity rate was varied from 0 to 90% in a cell by setting exposure times of 15 min and device characterized, followed to 15 min vacuum. Secondly, humidity rate is fixed at 90% during 144 min and the electrical characteristics recorded successively. The main electrical parameters such as threshold voltage (VT), mobility (μ), on-current (Ion), depletion current (Ioff) and subthreshold slope (S) have been investigated. The results showed that only the electrical parameters in subthreshold region have been affected at different relative humidity (RH) levels for the first series. Under vacuum, the device exhibited stable electrical performances whereas in RH ranging from 24% to 90% we observe an increase of depletion current, and this Ioff increase was found to be reversible. After exposing the device with 90% of RH (second series), from 0 to 108 min in humid environment, threshold voltage, Ion current, VT and charge carrier mobility remain unchanged while Ioff and S are highly affected. Beyond 108 min, Ioff current keeps increasing with a noticeable Ion current degradation. Two effects have to be taken into account: (i) Ioff current increase without any change in on-state regime is the consequence of cumulative effect of Leakage current increase in the parylene dielectric and electrical conductivity increase in pentacene semiconductor, (ii) Ion current decrease is the consequence of absorbed water molecule diffusing and interacting with pentacene. All these parameters are reversible under vacuum after pumping down.

Inkjet-Printed Oxide Thin-Film Transistors Based on Nanopore-Free Aqueous-Processed Dielectric for Active-Matrix Quantum-Dot Light-Emitting Diode Displays.

Inkjet-printed thin-film transistors (TFTs) for active-matrix light-emitting diode display are drawing much attention for the advantages of low material waste and simple fabrication processes without vacuum deposition and photolithography steps. Herein, for the first time, solution-processed quantum-dot light-emitting diode (QLED) array displays driven with the inkjet-printed oxide TFT backplane were realized and demonstrated using a general "solvent printing" method. To suppress nanopore formation in the thick oxide films, carbon-free aqueous inks were employed for gate dielectrics. No nanopore was found in the whole 120 nm-thick gate dielectrics. However, compared to the organic inks, the aqueous inks have very low viscosity, resulting in uncontrollable ink spreading especially in transline printing. The ink easily shrinks on the low-surface-energy area and spreads on the high-surface-energy area, leading to serious uniformity problems (the upper lines even break at the top of underlying lines). To solve the problem, a "solvent printing" method was employed to form coffee-line surface-energy patterns, which were uniform without shape distortion. The surface-energy patterns can restrain the ink spreading and tune the morphology of the printed films. As a result, multilayer TFT arrays with ideal shapes were achieved. The mobilities of the printed top-gate TFTs in the backplane array were 3.13 ± 0.87 cm2 V-1 s-1 for switching TFTs and 2.22 ± 0.38 cm2 V-1 s-1 for driving TFTs. Finally, an active-matrix red QLED character display based on the printed oxide TFT backplane and solution-processed QLEDs was demonstrated. The "solvent printing" method opens a general route for inkjet-printed multilayer electronic devices.

Quantitative analysis of interface trap recovery caused by repetitive bending stress in flexible oxide thin-film transistors

We quantitatively characterized the thermal recovery process of flexible top-gate amorphous InGaZnO thin-film transistors stressed by repetitive mechanical bending. The interface trap density increases due to repetitive bending stress concentrated at the interface between the InGaZnO and Al2O3 layers near the source and drain electrodes. After 40 000 bending cycles, an increase in series resistance and subthreshold slope degradation is observed. Then, the restoration of the subthreshold slope is monitored over several hours at elevated temperatures. The threshold voltage remained nearly constant during this process. We propose a stretched exponential approach to the time-dependent subthreshold slope restoration to quantify the recovery of interface trap density at various temperatures. We present the method to extract the activation energy required for thermal relaxation of the interface trap sites generated by repetitive bending stress.

Depth-profiling XPS analysis of He-plasma treated amorphous InGaZnO thin films for use in top-gate coplanar thin-film transistors

A low-resistance amorphous InGaZnO (a-InGaZnO) film obtained with helium (He) plasma treatment is commonly used as the source/drain regions of top-gate planar thin-film transistors. Here we discuss some experimental results for the low-resistance a-InGaZnO films, focusing on depth profiling analysis of X-ray photoelectron spectroscopy signals. We show that the effect of He plasma treatment, which is generation of considerable oxygen vacancies, extends for the entire thickness (over 70 nm) of a-InGaZnO film. We also show that a significantly In-rich layer may be formed beneath the a-InGaZnO surface, depending on the He plasma power density.

All-Sputtering, High-Transparency, Good-Stability Coplanar Top-Gate Thin Film Transistors

In this work, transparent, stable coplanar top-gate thin film transistors (TFTs) with an active layer of neodymium-doped indium oxide and zinc oxide (Nd-IZO) were successfully fabricated on a glass substrate by all sputtering processes. The devices with a post-annealing temperature of 400 °C exhibited good electrical performances with a saturation mobility (μsat) of 4.25 cm2·V−1·S−1, Ion/Ioff ratio about 106, Vth of −0.97 V and SS about 0.34 V/decade. Furthermore, the devices exhibited excellent negative and positive bias stability (NBS, PBS) of only a ΔVth shift of about −0.04 V and 0.05 V after 1 h, respectively. In addition, the devices showed high transparency about 96% over the visible-light region of 400–700 nm, which indicates a great potential in transparent displays.

Development of oxide thin-film transistor using all spin-on-glass insulators with addition of hydrogen peroxide: Buffer, gate insulator, and interlayer dielectric

A top-gate oxide thin-film transistor (TFT) with all spin-on-glass (SOG) insulators was developed. The SOG is based on methyl siloxane and was used for the buffer layer, gate insulator, and interlayer dielectric instead of a vacuum process. The SOG was diluted with ethanol, and a small amount of hydrogen peroxide was added. The diluted SOG was applied to top-gate amorphous indium–gallium–zinc-oxide TFTs, and the effects of the dilution and the hydrogen peroxide added were investigated. The TFTs with the optimized SOG insulators showed a mobility of 7.1 cm2/(V·s), a threshold voltage of 0.5 V, a subthreshold slope of 0.1 V/dec, and an on/off current ratio of 3.6 × 107.

Flexible In–Ga–Zn–O Thin-Film Transistors With Sub-300-nm Channel Lengths Defined by Two-Photon Direct Laser Writing

In this paper, the low-temperature (≤150 °C) fabrication and characterization of flexible indium–gallium–zinc–oxide (IGZO) top-gate thin-film transistors (TFTs) with channel lengths down to 280 nm is presented. Such extremely short channel lengths in flexible IGZO TFTs were realized with a novel manufacturing process combining two-photon direct laser writing (DLW) photolithography with Ti/Au/Ti source/drain e-beam evaporation and liftoff. The resulting flexible IGZO TFTs exhibit a saturation field-effect mobility of 1.1 cm $^{\textsf {2}}\cdot \textsf {V}^{-\textsf {1}}\cdot \text {s}^{-\textsf {1}}$ and a threshold voltage of 3 V. Thanks to the short channel lengths (280 nm) and the small gate to source/drain overlap ( $5.2~\mu \text{m}$ ), the TFTs yield a transit frequency of 80 MHz (at 8.5-V gate–source voltage) extracted from the measured S-parameters. Furthermore, the devices are fully functional when wrapped around a cylindrical rod with 6-mm radius, corresponding to 0.4% tensile strain in the TFT channel. These results demonstrate a new methodology to realize entirely flexible nanostructures and prove its suitability for the fabrication of short-channel transistors on polymer substrates for future wearable communication electronics.

Difluorobenzothiadiazole and Selenophene-Based Conjugated Polymer Demonstrating an Effective Hole Mobility Exceeding 5 cm2 V-1 s-1 with Solid-State Electrolyte Dielectric.

We report synthesis of a new poly(4-(4,4-bis(2-ethylhexyl)-4 H-silolo[3,2- b:4,5- b']dithiophene-2-yl)-7-(4,4-bis(2-ethylhexyl)-6-(selenophene-2-yl)-4 H-silolo[3,2- b:4,5- b']dithiophene-2-yl)-5,6-difluorobenzo[ c][1,2,5]thiadiazole (PDFDSe) polymer based on planar 4,7-bis(4,4-bis(2-ethylhexyl)-4 H-silolo[3,2- b:4,5- b']dithiophen-2-yl)-5,6-difluorobenzo[ c][1,2,5]thiadiazole (DFD) moieties and selenophene linkages. The planar backboned PDFDSe polymer exhibits highest occupied molecular orbital and lowest unoccupied molecular orbital levels of -5.13 and -3.56 eV, respectively, and generates well-packed highly crystalline states in films with exclusive edge-on orientations. PDFDSe thin film was incorporated as a channel material in top-gate bottom-contact organic thin-film transistor with a solid-state electrolyte gate insulator (SEGI) composed of poly(vinylidene difluoride-trifluoroethylene)/poly(vinylidene fluoride- co-hexafluroropropylene)/1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, which exhibited a remarkably high hole mobility up to μ = 20.3 cm2 V-1 s-1 corresponding to effective hole mobility exceeding 5 cm2 V-1 s-1 and a very low threshold voltage of -1 V. These device characteristics are associated with the high carrier density in the semiconducting channel region, induced by the high capacitance of the SEGI layer. The excellent carrier mobility from the PDFDSe/SEGI device demonstrates a great potential of semiconducting polymer thin-film transistors as electronic components in future electronic applications.

Lowering interface state density in carbon nanotube thin film transistors through using stacked Y2O3/HfO2 gate dielectric

Wafer-scale fabrication of transistors is the prerequisite for practical applications of carbon nanotube (CNT) based electronics. In this work, we fabricated top-gated thin film transistors (TFTs) based on solution-derived CNT film prepared on a 2 in. substrate through a photolithography based process. In particular, we improved the gate dielectric layer in CNT TFTs through using a thin thermal oxidized Y2O3 film as a buffer layer before the growth of high-κHfO2 layer. The introduction of the Y2O3 film significantly enhanced the performance of CNT TFTs, including the improved on-state current and transconductance, lowered threshold voltage and subthreshold swing, and drastically enhanced carrier mobility, owing to the reduction of the interface state density and scattering centers. Quantitative extraction of the interface state density based on either capacitance-voltage measurements or subthreshold swing data further demonstrates that the introduction of the Y2O3 interlayer reduces the interface state density from 9.24 × 1012 cm−2 to 4.63 × 1012 cm−2 in the gate insulator.