Channel-protecting fabrication of top-gate MoS2 transistor arrays

Abstract

The surface passivation on MoS2 and other transition metal dichalcogenides (TMDs) has been widely studied and utilized to prevent contamination and oxygen/water vapor penetration. Such approaches are mostly applied on the back-gate transistors after the formation of source/drain electrodes, while the compatibility in constructing top-gate devices has not yet been experimentally explored. Here, based on the large-area MoS2 thin film prepared with the atomic layer deposition technique, we developed an experimental routine to fabricate top-gate MoS2 thin-film transistor arrays with the TMD channel protected by high-k dielectric during the entire device fabrication process. The channel protection is enabled by the high-quality Al2O3 dielectric with proper pretreatment. The transistors in the array have shown enhanced electrical performance compared to the non-protected devices. Such a robust and well-controlled fabrication technique is a typical case of developing functional electronic devices by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth, which can be further extended to the wide application in higher-level systems based on TMD materials.