Short-Channel Top-Gate InGaZnO Thin-Film Transistors Fabricated With Boron Implantation Into Source/Drain Regions

Abstract

In this brief, we discuss top-gate InGaZnO thin-film transistors (InGaZnO TFTs) fabricated with boron (B) implantation into the source–drain regions, focusing on channel shortening. B was implanted through the gate insulator into the InGaZnO layer. From scanning capacitance microscopy (SCM) analysis, we found that boron implantation in the S/D regions of InGaZnO TFTs induces channel shortening. We also found that such channel shortening is suppressed by optimizing acceleration voltage in the boron implantation process, leading to good operation in short-channel ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5~\mu \text{m}$ </tex-math></inline-formula> ) InGaZnO TFT.