Abstract
We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (R SD ) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced R SD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation, realized further R SD reduction. In addition, threshold voltage (V th ) controllability by back-gate bias was enhanced by adopting thin InGaZnO body and BOX. Successful applications of these booster technologies developed for Si LSIs enable us to fabricate high-performance top-gate scaled InGaZnO TFT in 3D LSI.
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