Channel Thickness Research Articles

Enhancing the Stability and Mobility of TFTs via Indium-Tungsten Oxide and Zinc Oxide Engineered Heterojunction Channels Annealed in Oxygen Ambient.

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium-tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility.

A physics based model for negative capacitance TFET considering variation in ferroelectric parameters

Here, an explicit analytical model of electrical properties like channel potential, electric field, drain current, and threshold voltage for a negative capacitance DGTFET structure is developed. The model properly calculates the channel potential profile by solving the Poisson equation using the Landau-Khalatnikov (LK) model (for incorporating the NC effect). The electric field expression is developed using a channel potential model. The drain current expression is obtained by mathematically integrating the rate of band-to-band tunneling generation over the channel thickness. The threshold voltage has been derived using a method called maximal trans-conductance. Furthermore, by varying the FE parameters like thickness (t fe ), coercive field (E C ), and residual polarization (P R ), we improve capacitance matching and gate control of the device. All of the model results demonstrated a perfect alignment with those discovered by TCAD simulations. Designing devices and circuits for low-power applications can be more effective from these results.

Multi-U-Style micro-channel in liquid cooling plate for thermal management of power batteries

In order to cope with the problem of the shortening of automotive power battery life and the reduction of occupant safety due to the large amount of heat generated by automotive power batteries of high-energy–density at high discharge rates, this paper proposes a Multi-U-Style micro-channel in the liquid-cooled plate (Multi-U), based on the heat generation characteristics and temperature distribution of automotive power batteries. The impact of different Multi-U arrangements on the cooling performance of the batteries is explored, and the results indicate that the cooling performance is better with the side face arrangement. Compared to main face 1, the maximum temperature (Tmax) and maximum temperature difference (ΔTmax) of the batteries decrease by 2.40 K and 2.50 K, respectively. In addition, through a comparative analysis with typical serpentine micro-channel chilled plate (SMCP) and parallel micro-channel chilled plate (PMCP), Multi-U exhibits superior overall performance. Furthermore, the influence of equally incremental and decreasing channel width of Multi-U from the center to the periphery on cooling performance of the batteries is explored. It turns out that when the channel width is equally decreasing 1 mm Multi-U (D 1 mm), the heat dissipation is most effective. Finally, the critical parameters of the Multi-U are optimized to improve the power density of batteries. The impact of critical parameters of the Multi-U on the cooling performance of the batteries is studied through orthogonal experiments. The optimal parameter combination is found to be a channel width (W) = 12 mm, channel thickness (H) = 6 mm, inlet mass flow rate (F) = 0.02 kg∙s−1, and inlet coolant temperature (T) = 292.15 K. Compared to the original Multi-U, the Tmax and ΔTmax of batteries decrease by 5.83 K and 0.06 K, respectively, while the pressure drops decrease by 89 %.

Design and performance analysis of double gate vertically stacked MoS2 nanosheet field effect transistor

In this work we report a vertically stacked nanosheet Field Effect Transistor (NSFET) in double gate configuration using transition metal dichalcogenide (TMD) based molybdenum disulphide (MoS2) as the conducting channel. The performance of the NSFET is analysed for number of channels, different channel thickness, different source/drain contacts. The performance of the device at different temperatures (T) also analysed. The proposed NSFET with three vertically stacked channels, exhibits a ON current (ION) of 30.6 μA μm−1, Subthreshold swing (SS) of 69 mV/dec and ON to OFF current ratio of more than 108 at Vds = 1V. Further the ION can be improved with multi-layer channel thickness. The performance of the vertically stacked MoS2 NSFET in junction less (JL) and inversion mode (IM) is compared, it is concluded from the simulations that JL vertically stacked MoS2 NSFET more immune to short channel effects such as threshold voltage (Vth) roll-off and drain induced barrier lowering (DIBL).

High-Performance WS2 MOSFETs with Bilayer WS2 Contacts.

WS2 is a promising transition-metal dichalcogenide (TMDC) for use as a channel material in extreme-scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its monolayer thickness, high carrier mobility, and its potential for symmetric n-type and p-type MOSFET performance. However, the formation of stable, low-barrier-height contacts to monolayer TMDCs continues to be a challenge. This study introduces an innovative approach to realize high-performance WS2 MOSFETs by utilizing bilayer WS2 (2L-WS2) in the contact region grown through a two-step chemical vapor deposition process. The 2L-WS2 devices demonstrate a high I ON/I OFF ratio of 108 and a saturated drain current, I D(SAT), of 280 μA/μm (386 μA/μm) at room temperature (78 K), even while still using conventional metal (Pd or Ni) contacts. Devices featuring a 1L-WS2 channel and 2L-WS2 in the contact regions were also fabricated, and they exhibited performance comparable to that of 2L-WS2 devices. The devices also exhibit good stability with nearly identical performance after storage over a 13 month period. The study highlights the benefits of a hybrid channel thickness approach for TMDC transistors.

Device and Noise Performances of AlGaN/GaN High Electron Mobility Transistors with Various GaN Channel Layers Grown on AlN Buffer Layer

AlGaN/GaN high electron mobility transistors (HEMTs) with different GaN channel layers grown on AlN buffer layer are fabricated and investigated in order to optimize the device performances and to study the noise properties. To investigate the strain effect of the GaN channel layer grown on the AlN buffer layer, the positive shift of Raman peak is observed as the GaN channel becomes thinner. The threshold voltages (Vth) of the fabricated devices shift to positive direction according to the decreased GaN channel layer due to the decreased 2‐dimensional electron gas (2DEG) and deteriorated crystal quality of GaN channel layer. All devices demonstrated 1/f noise properties and the dominance of the carrier number fluctuations (CNF) noise mechanism. The largest trap density (Nt) value in the narrowest GaN channel device is because of the degraded crystal quality and the enhanced strain effect of the GaN channel layer. However, the lowest noise levels at the drain current (Id) > 10−6 A for the device with the GaN channel thickness of 30 nm grown on AlN buffer layer are observed to be due to the fully depleted GaN channel layer although its poor crystal quality.

Performance optimization of AlGaAs and Al x Ga 1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

This study aims to enhance the efficiency of the Double Gate-Junctionless-Tunnel Field Effect Transistor (DG-JL-TFET) by optimizing the utilization of AlGaAs and GaAs/Si/AlGaAs-based Single Material and Tri-Material (SM and TM) configurations.In order to overcome the drawbacks of present TFET architectures, such as their limited ability to drive current and their ambipolar behaviour, and to enhance the on-state current, To execute our suggested SM-TM-DG-JL-TFET configuration. The TM structure exhibits a greater on-state current (I on ) and a lower SubthersholdSwing (SS) in comparison to SM structures. This study quantifies the Unit-gain-current-cut-off-frequency (f t ) and Maximum oscillation frequency fmax by manipulating geometric parameters such as gate length(l g ), gate-oxide thickness, and Channel thickness. The TM structure exhibits a significantly greater on-state current (I on ) of 14 × 10−3 A. Compared to SM structures, while simultaneously reducing the off-state current (I off ), subthreshold swing (SS), and threshold voltage (V t ). TM structures exhibit higher values of f t and fmax in DG-JL-TFET due to their enhanced output conductance compared to SM structures. The device exhibits potential for future low-power-RF applications due to its significant values of f t and fmax .

Numerical Investigation of the Irreversible Behavior of GDL Under Cyclic Hygrothermal Loading

Performances of proton exchange membrane fuel cells (PEMFCs) is impacted by the physical properties of the gas diffusion layer (GDL). These properties, including thickness and porosity, are irreversibly modified by diverse processes, notably by the clamping of the PEMFC or the swelling of the membrane during cell operation. This can result in irreversible deformation of the GDL, with consequent impact on the performance and durability of the PEMFCs. This phenomenon, which is difficult to apprehend experimentally, is also challenging to investigate numerically. An elastoplastic law related to the irreversible strain of the GDL after compression is proposed in this study and implemented in a finite element model. Variations in GDL’s properties during humidity and temperature cycles are studied depending on PEMFC clamping methods using numerical simulations. The influences of processing conditions, i.e. the membrane electrode assembly hot pressing process, on GDLs properties are also investigated numerically. The results demonstrate the necessity to take into account the evolution of the mechanical properties of PEMFC components, with a significant influence of clamping process, life load and hot pressing process on the physical properties of the GDL as thickness, porosity, or intrusion in the gas channels.

P‐12: Improve the Reliability of a‐IGZO TFT through Optimizing the Threshold Voltage and Channel Thickness in AMOLED Hybrid Backplane

In the fabrication of flexible a‐IGZO and LTPS thin film transistor (TFT) hybrid backplane, various threshold voltage (Vth) of the a‐IGZO TFT was achieved in this paper by regulating the O2/Ar ratio during the deposition of a‐IGZO film by sputtering. The results show that the Vth increases with the increase of the O2/Ar ratio, and the reliability tests indicate that in a certain range negative adjustment of Vth can significantly improve the positive bias temperature instability (PBTI) of IGZO TFT, and maintain good electrical uniformity. The increase of the O2/Ar ratio reduces the number of oxygen vacancy (Vo) in the a‐IGZO channel, and thereby Vth is positively shifted, which is confirmed by the TCAD simulation. The Vth value can indicate the Vo concentration in a‐IGZO TFT channel partly, and appropriately higher amount of Vo is beneficial to improve the PBTI, which is attributed to Fermi level (EF) shifting closer to conduction band. Raised EF means less unoccupied trap states, resulting in less carrier trapping under PBTI. Furthermore, the research also explores different a‐IGZO channel thicknesses and finds that when the Vth values are similar, thinner channel layers endow a‐IGZO TFT with improved PBTI. By optimizing the Vth and channel thickness, a‐IGZO TFTs with a channel thickness of 25nm and a Vth value of 0.2V have been prepared in a hybrid backplane. Under positive bias temperature stress for 5 hours, the Vth is positively shifted less than 0.5 V, which could lay the foundation for achieving high‐reliability flexible backplane for AMOLEDs.

Channel thickness effect on the performance of amorphous SiZnSnO semiconductor thin-film transistor with metal capping structure

Channel thickness effect on the performance of amorphous SiZnSnO semiconductor thin-film transistor with metal capping structure

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (t FE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher t FE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.

Correlation between CO2 Sensitivity and Channel-Layer Thickness in In2O3 Thin-Film Transistor Gas Sensors

CO2 monitoring is important for achieving net-zero emissions. Here, we report on a CO2 gas sensor based on an In2O3 thin-film transistor (TFT), which is expected to realize both low-temperature operation and high sensitivity. The effect of channel thickness on TFT performance is well known; however, its effect on CO2 sensitivity has not been fully investigated. We fabricated In2O3 TFTs of various thicknesses to evaluate the effect of channel thickness on CO2 sensitivity. Consequently, TFT gas sensors with thinner channels exhibited higher CO2 sensitivity. This is because the surface effect is more prominent for a thinner film, suggesting that charge transfer between gas molecules and the channel surface through gas adsorption has a significant impact on changes in the TFT parameters in the subthreshold region. The results showed that the In2O3 TFT in thin channels is a promising candidate for CO2-sensitive TFT gas sensors and is useful for understanding an effect of gas adsorption in oxide TFTs with a very thin channel as well.

Achieving Near‐Ideal Subthreshold Swing in P‐Type WSe2 Field‐Effect Transistors

AbstractThe pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months.

Exploring Intertwined quantum and cryogenic behaviour in ultra-scaled 10 nm MOSFET: a NEGF quantum ballistic simulation

Silicon-based spin qubits have emerged as promising candidates for scalable quantum information processing. This study first time investigates the behaviour of ultra-scaled 10 nm gate length and 3 nm channel thickness nanoscale double gate metal-oxide semiconductor field-effect transistors (MOSFETs) over a broad temperature range, from deep cryogenic (4 K) to room temperature (300 K). Employing the Non-Equilibrium Green’s Function (NEGF) method, the research explores the intertwined quantum and cryogenic behaviours of the various quantum phenomena, including eigen energies, eigen-functions, electron concentration, current characteristics, and more. This comprehensive analysis sheds light on the intricate interplay of quantum effects in nanoscale transistors under deep cryogenic conditions, offering valuable insights into the development of cryo-CMOS circuits for quantum computing.

Impact of channel thickness on device scaling in vertical InGaZnO channel charge-trap memory transistors with ALD Al2O3 tunneling layer

This study investigates the impact of channel thickness (TCH) variation on memory performance and its physical origins in vertical channel charge trap memory (V-CTM) using InGaZnO (IGZO) channels for X–Y scaling. When the TCH decreased, the subthreshold slope (SS) increased from 0.21 to 0.30 V/dec, while the minimum program voltage decreased from 12 to 8 V, indicating a performance trade-off. The analysis of bulk trap density extracted by SS, density of states distribution, and x-ray photoelectron spectroscopy confirmed an increase in the number of trap states and hydrogen-related defects in the IGZO channel when a thin TCH is employed. As a result, it was expected that the barrier height at the active layer/TL would be lowered during program operations at relatively thin channel. However, the SS would also be degraded due to an increase in sub-gap states, such as OH- and VOH, induced by hydrogen incorporation. The V-CTM with an optimal TCH of 7 nm had a maximum memory window of 5.7 V. The program/erase states were maintained for 106 s before experiencing a 50 % charge loss, and 5-level memory states were verified to be available within a memory window of 3.2 V for 108 s with little degradation. It was noteworthy that the long-term reliability and multilevel implementation could be secured for the V-CTM with a TCH as thin as 7 nm, demonstrating the sound feasibility of its X–Y scaling. This work presents new key parameters and understanding of device integration issues for future 3D structured memory transistors, and aims to contribute to the advancement of memory technologies using oxide semiconductor channels.

Promotion of Processability in a p-Type Thin-Film Transistor Using a Se-Te Alloying Channel Layer.

p-type thin-film transistors (pTFTs) have proven to be a significant impediment to advancing electronics beyond traditional Si-based technology. A recent study suggests that a thin and highly crystalline Te layer shows promise as a channel for high-performance pTFTs. However, achieving this still requires specific conditions, such as a cryogenic growth temperature and an extremely thin channel thickness on the order of a few nanometers. These conditions critically limit the practical feasibility of the fabrication process. Here, we report a high-performance pTFT incorporating a 60-nm-thick highly crystalline Se-Te alloyed channel layer, produced using pulsed laser ablation at room temperature. The Se0.5Te0.5 alloy system enhances crystalline temperature and widens the band gap compared to a pure Te channel. Consequently, this approach results in a field-effect mobility of 3 cm2/V·s, with an on/off current ratio of 3 × 105, a subthreshold slope of 2.1 V/decade, and a turn-on voltage of 6.5 V, achieved through conventional annealing at 250 °C. To demonstrate its applicability in complementary circuit applications, we integrate a complementary-type inverter using a p-type Se0.5Te0.5 TFT and an n-type Al-doped InZnSnO, demonstrating a high voltage gain of 12 and a low static power consumption of 17 nW. This suggests that the Se-Te alloyed channel approach paves the way to a more straightforward and cost-effective process for Te-based pTFT devices and their applications.

Sensitivity Analysis and Optimization of Heat Transfer Performance of Ultra-Thin Vapor Chamber With Composite Wick

Abstract An ultra-thin vapor chamber (VC) with the composite wick formed by four spiral woven meshes (SWMs) and a copper mesh was proposed to solve the heat dissipation problem in miniaturized electronic equipment because of its sufficient heat transfer capability under limited thickness. However, the influence factors on the thermal performance of the VC with composite wick are more than that of the VC with a single type of wick. In this study, in order to investigate the thermal performance of the VC with composite wick, a theoretical model was developed to calculate the maximum heat transfer capacity. Besides, a three-dimensional numerical model for the heat transfer characteristics was established, and the simulation results have a good match with the experimental results. The orthogonal test method was adopted to determine that both the width of the vapor channel (wv) and the thickness of the vapor channel (tv) have a significant effect on the maximum heat transfer capacity and thermal resistance, while the porosity of the mesh (εmesh) has a prominent effect on the maximum heat transfer capacity, but has little effect on the thermal resistance. Further optimization of the sensitive factors for VC heat transfer performance was achieved to enhance the maximum heat transfer capacity.

A Stretchable Thermoelectric Device based on Direct Ink Writing of Liquid Metal and Multi‐Layer Lamination

AbstractWearable thermoelectric devices are widely used due to their ability to generate heat and cool rapidly without the need for bulky external equipment. Researchers have explored methods to enhance flexibility and stretchability by incorporating liquid metal as an electrode. However, the challenge lies in the low thermal conductivity of the polymer, which hampers heating and cooling performance. Traditional methods, like molding and spraying, increase the thickness of both liquid metal and polymer channels, but this added thickness does not significantly improve the device's stretchability.[1, 2] To overcome these issues, this paper proposes a stretchable thermoelectric device (STED), which offers improved heating and cooling capabilities, as well as enhanced stretchability. To enhance the thermal conductivity of the polymer, Ag powder with varying particle sizes is mixed with the material. Additionally, the liquid metal is deposited using the direct ink writing (DIW) method, reducing the whole thickness of STED. The air layer is created by printing molten isomalt, which is subsequently removed using water. The proposed STED exhibits high stretchability, reaching up to 150 %, enabling flexible twisting in various directions. The double‐layer structure resulted in a maximum temperature decrease of 14 °C at room temperature.

Numerical investigation of cold formed steel sleeve connection for channel sections subjected to combined bending and shear

This study focuses on the behaviour of the sleeve connection to ensure proper distribution of moment at the location of discontinuity between two channel sections subjected to combined bending and shear using finite element (FE) modelling. The FE model was validated with the experimental data from previous authors studies and was found. A total of 180 simulations were carried out as part of the parametric study, by varying the depth, thickness, length of sleeve connector, length of the test specimen, and bolt configuration. Two modes of failure were identified based on sleeve length (Ls) and combination of sleeve length and channel thicknesses. The Ls/D ratios were suggested to achieve a similar strength and stiffness of sleeve specimen when compared with control specimen. The influence of sleeve length on the ultimate moment resistance was studied for combination of sleeve length and channel thickness. The increase in the channel thickness from 2 mm to 2.5 mm led to as significant increase in the ultimate moment resistance. An equation was proposed to calculate the nominal moment capacity of sleeved specimens and reliability analysis of this equation was carried out. The conservativeness of the proposed design procedure was checked by comparing it with the AISI S100 [1] interaction curve.

Numerical investigation of switchable cooling-heating-power trigeneration system based on flow channel control in summer

In this study, a numerical model is proposed via MATLAB software to respond to the dynamic indoor heating and cooling loads. This model combines spectral splitting PV/T systems and sky radiative cooling to achieve switchable heating, cooling, and electricity harvesting. Especially in the summer, the application of sky radiation cooling technology can lower the energy consumption of buildings. Meanwhile, the outdoor parameters and the operating factors are studied to explore the effects on the electric power and cooling power. Results indicate the threshold value of solar radiation for running daytime mode or nighttime mode is vital to output performance, and the optimal threshold value is recommended as 150W/m2 to regulate the switchable system. The flow velocity affects the convective heat transfer effects between the flowing water and the glass. As the flow velocity increases from 0.0005m/s and 0.0040m/s, the mean electric power improves from 41.3W to 54.1W and the cooling power improves from 62.6W to 96.4W respectively. Hence, it is suggested to employ a flow velocity of 0.0040 m/s to augment the system's capacity and adopt a channel thickness of 5mm, which can effectively reduce material costs without substantially compromising the power output.